high level synthesis with Xilinx

key notes:

• write your struct ASIC c code, no class...., only for struct supported
• familiar hardware c (no hierarchal ptr, dynamic/static cast/ptr)
• implemented module select(architecture set)
• sub standard cell assign
•  like a+b  for operator "add", it can be "32bitAdd", or "64bitAdd" ...
• memory assign
• internal buffer, (asyn_fifo) for different clock interface
• for loop extend(unroll)
• like for (i=0; i < 2; i++), it will be extend to l0, l1, sequences for reschedule, if the data doesn't have any dependence in this loop, that can merge these two sequences in one parallel sequence. 
• resource constrain
• area constrain
• sub cell constrain
• timing constrain
• scheduling and binding
• pipeline
• implemented protocol interface
• AXI3/4 AXI stream
• transfer task assign
• req/grant
• burst ... ex: axi_bus_write(addr, [data,..]) => for axi burst write transfer 

• RTL code gen
• verilog/systemc
• report
• trade off
• performance/area
• simulation time estimation
• delay 
• area estimation
• size
• refs:
• http://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_2/ug902-vivado-high-level-synthesis.pdf
• http://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_2/ug871-vivado-high-level-synthesis-tutorial.pdf
• http://www.xilinx.com/support/answers/50929.html