UVM guide line

• Naming rule
• axi_package, axi_monitor.svh
• how to debug
• if (debug) `uvm_info("DEBUG", msg, UVM_MEDIUM)
• uvm_factory  factory = uvm_factory.get(); factory.print();
• uvm_top.print_topology()
• how to trace connection 
• use "get_connect_to()", "get_provide_to()", children[$]
• 
  // If there is something connected,
  // print the port name and the connections. 
  if ((connected_to_list.size() > 0) || (provided_to_list.size() > 0) ) begin 
  // Print the name of the port. $display("%s Port: %s", {depth+2{" "}},
  children[i].get_full_name()); end 
  
• how to trace transactions
• use backdoor to log the analysis point
• fifo.put_export.debug_connected_to(); fifo.put_export.debug_provided_to();
• $display("%s", tx_queue[tx_id].convert2string());
• atomic transaction items(active sequence)
• use "pre_body()" phase to add new sequence
• use "post_body()" phase to remove sequence
• active_sequenves::show();
• internal BB(break) point(assertion pp)
• `define BB if (BB::check_pp1( tx, get_full_name()) $stop;
• use "grep" command to filter out the useful info
• grep "type_id::create" xx.log
• use report catcher without default UVM_report, collect the report pool meg to our report format
• function action_e catch();
• id = get_id(); 
• filename = get_fname(); 
• line = get_line(); 
• severity = get_severity();
• $dispay("%s...,", id);
• use report server to overwrite the report

ref: Better Living Through Better Class-BasedSystemVerilog Debug

UVM notes 1

• Ref:
• UVM reference flow
• UVM tutorial
• http://cluelogic.com/tag/vmm/UVM_AGENT
• 
  
• transaction and sequence
• transactions level info
• collect pin level info to transaction package info, like AXI, req, data, reps, phase for one valid transaction


• sequence
• a lots of transactions
• read/write with burst/2D ...
• ex:
• jb_tx = jelly_bean_transaction::type_id::create(.name('jb_tx'), ...); 
• #create transaction
• start_item(jb_tx);
• #start transaction and send it to sequence_item
• finish_item(jb_tx);
• # end of transaction
• agent
• verification module that contains
• monitor module(collect transaction)
• sequencer module(sequence_item handler)
• driver module(drive transaction to virtual interface)
• ex: 
• jb_ap = new(.name('jb_ap'). parent(this));
• jb_seqr = jb_sequencer::type_id::create(.name('jb_seqr'), .parent(this));
• jb_drvr = jb_driver::type_id::create(.name('jb_drvr'), .parent(this));
• jb_mon = jb_monitor::type_id::create(.name('jb_mon'),.parent(this));
• #build up each sub modules  @build_phase
• 
  
• jb_drvr.set_item_port.connect(jb_seqr.seq_item.export);
• jb_mon.jp_ap.connect(jb_ap);
• #connect ports and interface @connect_phase
• 
  
• #check conf(RGM) and interface is ok @build__phase or end_of_elaboration_phase
• environment
• build up test env 
• Agents
• Scoreboard
• record/check each transaction from master to slave is correct, if the transaction is error or out of time. show up some UVM_ERROR message to log file. 
• ex:
•   if (  !find_tx_in_jb_queue(tx) ) `uvm_error("trs not found..")
• package  
• build up 'import package' for each protocol or special purpose.
• `include "axi_driver.sv"
• ....
• `include "axi_env.sv"
• ex:
• import AXIPacakge::* #AXI standard protocol 
• test_lib
• build up test env 
• configure set
• address range
• register fields
• ex:
• uvm_config_db#(jelly_bean_configuration)::set
•            (.cntxt(this), .inst_name("*"), .field_name("config"), .value(jb_cfg));
• analysis_port(binding analysis port to analysis_export)
• easily to analysis and trace
• systemverilog tlm package socket to systemc socket
• analysis_port, analysis_export
• ex:
• jb_ap.write(jb_tx);
• # write transaction to analysis port
• jb_ap.connect(jb_sub.analysis_export)
• # connect analysis port to export in connect phase


• 
  

ECO tool for NetList Verilog

hi all,

if your are a CAD Engineer in IC design house, i think you always take a lot of time to do recourse jobs... like reassign wire names, add new cells, check netlist...that's really suck things. why not try this tool that can help you insert ECO cell automatically, and double check the ECO cell inserted is ok when you running this script.

features
1. ECO cell insert
2. ECO cell check
3. Module output Fanin check
4. Module input Fanout check
5. cell, port, net, width check

more to do
1. support Graph alg(NetworkX)
2. support assign statement
3. support STA, Timing check
4. support simulation???

Example:
Definition about input/output, ECO file...

# our org NetList file
        vtest = \
"""
module TOP( in, out );
input [1:0] in;
output [1:0] out;
INVD1 U0( .I( in[0] ), .ZN( out[0] ) );
INVD1 U1( .I( in[1] ), .ZN( out[1] ) );
endmodule
"""

# our cell lib file
        ytest = \
"""
AN2D1:
  inputs:
    A1: 1
    A2: 1
  outputs:
    Z: 1
  primitive: A1 and A2

INVD1:
  inputs:
    I: 1
  outputs:
    ZN: 1
  primitive: not I
"""

# our ECO file description, define where is the Input, Output link coming from, and it's assign value
        etest = \
"""
AN2D1:
  inputs:
    A1: new_in
    A2: in[0]
  outputs:
    Z:  new_out
  primitive: A1 and A2
"""

# our expect value
        exptest = \
"""
module TOP( new_in, new_out, in, out );

    output [  1: 0 ] out;
    input  [  1: 0 ] in;
    input new_in;
    output new_out;

    AN2D1 ECO_AN2D1( .A1( new_in ), .A2( in[0]), .Z( new_out ) );
    INVD1 U0( .I( in[0] ), .ZN( out[0] ) );
    INVD1 U1( .I( in[1] ), .ZN( out[1] ) );
endmodule                                                                                                                                                                            
"""

How to run

    Add new ECO cell in org NetList file.
    >>> eco = ECO()                                                                                                                                                                  
    >>> eco.readYAML("test/gates.yml") # read cell libs
    >>> eco.readVerilog("test/Iface_test.gv") # read org verilog Netlist file
    >>> eco.link("Iface_test") # link top module
    >>> eco.checkDesign() # check pre load design is ok
    >>> eco.report()
    >>> eco.readECO("test/ECO.yml") # read eco file
    >>> eco.runECO() # run eco
    >>> eco.checkDesign() # recheck design again when the ECO is done
    >>> eco.report()
    >>> eco.writeVerilog("test/new_Iface_test.gv")

How to run unittest nosetests
project