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2014年2月9日 星期日

raspberry pi + microcontroller


  • RAM size 256/512 
    • http://openenergymonitor.blogspot.tw/2013/10/raspberry-pi-new-type-of-ram.html
  • FTDI USB 2 UART adaptor (JTAG) shared with GPIO
    • http://www.ftdichip.com/Products/Modules/RPi.htm
    • FT232 JTAG
      • https://github.com/progranism/FT232R-JTAG
      • https://github.com/dwelch67/raspberrypi/tree/master/armjtag
  • openOCD
    • JTAG driver
    • USB or the Parallel Printer Port (USB to rs232)
    • arm instruction disassembly
    • http://visualgdb.com/tutorials/arm/openocd/
    • http://openenergymonitor.blogspot.tw/2013/10/raspberry-pi-new-type-of-ram.html
  • mount JTAG with GDB(Eclipse)
    • http://www.ethernut.de/en/tools/eclipse/confdebug.html
  • convert arm assembly to c
    • Hex-Rays
    • https://www.hex-rays.com/products/decompiler/compare_arm0.shtml
  • bootloader

  • adafruit (extend hardware models,such as motor, led, mcu)
    • GPIO export
    • http://www.adafruit.com/
    • http://learn.adafruit.com/category/learn-raspberry-pi


  • 開發板教學
    • http://ruten-proteus.blogspot.tw/

2013年9月22日 星期日

xilinx HLS for OpenCV example



refs:
http://xilinx.eetrend.com/files-eetrend-xilinx/download/201305/3986-8011-xapp1167.pdf

2013年7月3日 星期三

xilinx axi bus traffic gen


  • AXI4/AXI-stream
  • dependent/independent transaction
  • initial ram
  • error interrupt/ status
    • command
    • data
    • debug
  • address gen
    • align
      • byte 64bit, 32bit...
    • un-align
      • offset
    • type
      • inc, wrap, fixed
  • data gen
    • mem data width
  • initial system set
    • NOP instruction for dummy loops
  • Test DUT performance
  • replay Bus transactions when the debugging mode is opened

  • ref:
  • http://www.xilinx.com/support/documentation/ip_documentation/axi_traffic_gen/v1_0/pg125-axi-traffic-gen.pdf

Xilinx Hierarchical_Design_Methodology


  • bottom up
    • in any conditions should been re-runed partition again
      • VHDL/ngc/ngd source changed
      • constrains changed
      • partition changed
      • fpga package changed
    • partition(split to small partitions)
      • cost, benefit trade off, such as timing area ...
    • black box(often used in Memory or fixed devices)
      • ngc, ngd
      • synthesis token 
        • black box syntax in your VHDL like transfer_on, transfer_off
    • minimal logic
      • small cells. DSP/RAM normal cells
    • advantage
      • incremental place routing to reduce synthesis time
      • no rerun again when it's non-touchable design  
    • disadvantage
      • the constrains need to be reseted in whole chip view, because in each sub constrains only has it's constrains setting, if some paths from source pad to internal block and this path can cross through two different constrain blocks, it means the sub constrains it seems does't work for this set.
    • partition file
      • PXML
        • synplify smxl2pxml or xilinx xst
    • pblock
      • reversed place & route block 
    • ngc 
      • partition cell lib
    • BoundaryOpt
      • two partition interfaces bridge
  • top down
ref:
  • http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_3/Hierarchical_Design_Methodology_Guide.pdf
  • http://www.xilinx.com/support/documentation/white_papers/wp386_Hierarchical_Design_Synopsys_Xilinx.pdf

2013年6月20日 星期四

xilinx AXI interconnect

key notes


  • cascade AXI bus if the input port > 4 (crossbar) multi to one
  • traffic gen for DDR protocol (align burst length to 8), from AXI 2 DDR 
  • example:
    • 16 streams of 1920x1080 60/75p video information with up to 32 bits/pixel can be handled by a single 64-bit DDR3 interface
    • VDMA
    • Test Pattern Generators (TPGs) 
    • Video Timing Control (VTC) 
    •  On-Screen Display (OSD) 
  • performance
    • 622MB/s 
    • 16 streams through memory, or nearly 9.95 GB/s (80 Gb/s)! This 18-port shared memory controller is used to support the 16 VDMA channels
    • a memory clock speed of 800 MHz (1,600 MHz data rate).The primary internal AXI4 slave interface of the memory controller is operated at 200 MHz, using an AXI4 data width of 512 bits, supporting a theoretical maximum data bandwidth of 12.8 GB/s

refs: http://www.xilinx.com/support/documentation/white_papers/wp417-Xilinx-AXI4-Interconnects.pdfhttp://www.xilinx.com/support/documentation/application_notes/xapp521_XSVI_AXI4.pdf
http://www.xilinx.com/support/documentation/ip_documentation/ug761_axi_reference_guide.pdf

2013年6月19日 星期三

high level synthesis with Xilinx

key notes:

  • write your struct ASIC c code, no class...., only for struct supported
    • familiar hardware c (no hierarchal ptr, dynamic/static cast/ptr)
  • implemented module select(architecture set)
    • sub standard cell assign
      •  like a+b  for operator "add", it can be "32bitAdd", or "64bitAdd" ...
    • memory assign
      • internal buffer, (asyn_fifo) for different clock interface
    • for loop extend(unroll)
      • like for (i=0; i < 2; i++), it will be extend to l0, l1, sequences for reschedule, if the data doesn't have any dependence in this loop, that can merge these two sequences in one parallel sequence. 
    • resource constrain
      • area constrain
      • sub cell constrain
      • timing constrain
    • scheduling and binding
      • pipeline
  • implemented protocol interface
    • AXI3/4 AXI stream
    • transfer task assign
      • req/grant
      • burst ... ex: axi_bus_write(addr, [data,..]) => for axi burst write transfer 

  • RTL code gen
    • verilog/systemc
  • report
    • trade off
      • performance/area
    • simulation time estimation
      • delay 
    • area estimation
      • size
  • refs:
    • http://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_2/ug902-vivado-high-level-synthesis.pdf
    • http://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_2/ug871-vivado-high-level-synthesis-tutorial.pdf
    • http://www.xilinx.com/support/answers/50929.html

2013年6月7日 星期五

speed up your simulation !!


  • keynotes
    • no waveform dump
    • no timing check
    • using unit delay
    • using virtual model without real physical model
    • atomic test like selftest/unittest
    • atomic integration test / merge only input/output modules in DUT
    • using two stage 0/1 info without 4 stage info 0/1/X/Z
    • using error count num to finish simulation (avoid a lots useless info)
    • using assertion to check functional value

ref:
https://www.google.com.tw/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&ved=0CDIQFjAA&url=http%3A%2F%2Fwww.bawankule.com%2Fverilogcenter%2Ffiles%2FDVCon_Sim_Increase_paper.pdf&ei=bkGnUcOnKMWTiAeZroD4Bg&usg=AFQjCNEyEYLFxQb5Qo8XnYa3gLKppuIobw&sig2=GPKPKLOpKTZ3K4rmwZ571A
http://www.cadence.com/Community/forums/t/24886.aspx
http://www.synopsys.com/Tools/Verification/FunctionalVerification/Pages/VCS.aspx
http://www.deepchip.com/items/0385-03.html
http://www.cadence.com/community/forums/T/23927.aspx

2013年5月27日 星期一

Xilinx ucf constrain notes

ucf constrain

  • timing constrain
    • input pad to first flip-flop groups
      • input offset
    • internal flip-flop to flip flop groups
      • period
    • out flip-flop to output pad groups 
      • output offset
    • clock
      • offset
      • duty
      • jitter
      • rotate
        • 90 
        • 180
        • 270
  • multi cycle path
    • from one clock dom to another clock dom
    • using async fifo to avoid the data missing issue
      • data valid
      • req fifo.empty/fifo.full
      • status
  • false path
    • not normal paths
    • -to
    • -from -to
    • -through
    • -from -through -to 
  • data path
    • normal paths
  • fanout
    • set maxfanout
  • DCM / DLL/ PLL
    • ECO div/mux
  • TNM (timing group)

  • pin assignment constrain
    • pad assignment 

  • slack
    • Slack (setup path): =  (requirement - (data path - clock path 
    • skew + uncertainty))
    • Slack (hold path): = requirement - (clock path skew + uncertainty - data path) 

2013年5月16日 星期四

adding performance monitor to your design

the UVM monitor can play not only a functional checker but also a performance checker which means, user can use it more quickly to find out where is their design bottleneck without waveform tracing. in this topic, we focused on how to use UVM monitor to point out the collected transactions had timing violation immediately when the simulation was running.

we write a UVM SystemVerilog "req happened until grant received" to our demo case.

 
// spawn sub procs(threads)                                                                                                       
task run_phase(uvm_phase);
  fork
    sent_req();
    sent_grant();

    collected_req();
    collected_grant();

    check_performance();
    check_protocol();
  join
endtask : run_phase


// sent req 
task sent_req();

  forever begin
    // random  wait ....
    repeat($urandom_range(8,16)) @(posedge m_vif.CLK);

    // sent req 
    `delay(conf.half_cycle);
    m_vif.REQ <= `TRUE;
    @(posedge m_vif.CLK);

    // wait until grant received
    while(!m_vif.GRANT) @(posedge m_vif.CLK);

    // free req 
    `delay(conf.half_cycle);
    m_vif.REQ <= `FALSE;
    @(posedge m_vif.CLK);

  end

endtask : sent_req


// snet grant
task sent grant();

  forever begin

    // sent unvalid grant
    `delay(conf.half_cycle);
    m_vif.GRANT <= `FALSE;
    @(posedge m_vif.CLK);

    // wait until req received
    while(!m_vif.REQ) @(posedge m_vif.CLK);

    // random wait ...
    repeat($urandom_range(8,16)) @(posedge m_vif.CLK);

    // sent valid grant to free req
    `delay(conf.half_cycle);
    m_vif.GRANT <= `TRUE;
    @(posedge m_vif.CLK);

  end

endtask : sent grant                                                                                                              


task collected_req();

  forever begin
     // @ neg edge check
      @(negedge m_vif.CLK iff m_vif.REQ);

      // assert only one fifo deep when req/grant case
      assert(m_trx_q.size() < 1);

      // collect trx
      TRX m_trx = new();
      m_trx.REQ = m_vif.REQ;
      m_trx.TIME = $time;
      m_trx_q.push_back(m_trx);

  end
endtask : collected_req


task collected_grant();

  forever begin
    // @ neg edge cehck
    @(negedge m_vif.CLK iff m_vif.GRANT);

    //assert the queue size must be 1, means the req has been stored in the queue
    assert(m_trx.q.size() == 1);

    // free queue
    m_trx_q.pop_front();

  end
                                                                                                                                  
endtask : collected_grant


task check_performance();
  forever begin
    // at each pos edge check
    @(posedge m_vif.CLK);

    //assert queue
    if (m_trx_q.size() == 1) begin
        if ($time - m_trx_q[0].TIME > conf.min_offset) begin
          `uvm_error(get_full_name(), {$psprintf("out of time %d"), conf.min_offset}, UVM_LOW)
        end else begin
          `uvm_error(get_full_name(), {$psprintf("req/grant seuence is not valid")}, UVM_LOW)
        end
    end
  end

endtask             

2013年5月8日 星期三

Microsemi BFM script language


  • a very useful script language for bus performance estimation and bus functional check
    • example:
      • # read B uart 0;
        Reading offset 0 of uart – data = 0x1c
        # write B uart 4 bb;
        Writing 0xbb to offset 4 of uart
        # read B uart 8;
        Reading offset 8 of uart – data = 0x28
        # write B mac 30 11;
        Writing 0x11 to offset 30 of mac
        # readcheck B mac 11;
        Reading offset 0 of mac
        Error: Expected data = 0x11, Actual data = 0x22
        Test Failed, with 1 error
          
          

      • 
        
      • advantage
        • simple 
        • error check 
      • disadvantage
        • no time stamp
          • maybe it use ASAP(as soon as possible) methodology to transfer transactions, it means masters or slaves are not in busy status, or fetch/push buffers not full
        • no atomic transfer
          • if valid/ready is not continuous in the burst transaction, the interlevel transactions will happened, 
          • like A1(4), A2(4), A1 has burst 4 trxs, A2 has burst 4 trxs.
            • A1(2), A2(2), A1(2), A2(2) => atomic transactions when the A1 or A2 has busy or error in the internal transaction.

    synplify + ise TCL xflow

    http://outputlogic.com/xcell_using_xilinx_tools/74_xperts_04.pdf https://github.com/dlitz/openmsp430/blob/master/core/synthesis/actel/synplify.tcl https://github.com/martinjthompson/VHDL-compare/blob/master/Synplify/rev_1/run_ise.tcl https://github.com/martinjthompson/VHDL-compare/tree/master/Synplify https://github.com/zakiali/pocket_corr/blob/master/pfb_core/SgIseProject.tcl