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2014年2月9日 星期日

carCV

purpose

car and lane detection example
ScreenShot

method

-lane detection
  • houghlines
  • houghlinesP
  • fitlines
-car detection
  • haar cascades

how to run it?

step1. get video source %python get_video.py
step2. lane detection %python detect_lane.py
step3. car detection %python detect_car.py
Ref

remote openCV with raspberry pi




this is an example about how to use remote object detection based on openCV and zeromq framework.

requirements

  • opencv(python) as cv(opencv) and cv2(numpy)
  • zeromq(python)
  • gevent(light weight switch)
  • knowledge about img process
  • profile, logging each stage mem and cpu time

method

  • Server
    • capture img
    • send img to clinet
    • wait for next command from client
    • update status by new command
  • Client
    • receive img
    • run all detection
    • build up a new command based on detection results

detections

  • face detect
  • circle detect
  • line detect
  • find attribute obj

how to run it?

  • python poll_camera.py (using cv to capture/show img via remote protocol)
  • python poll_camera2.py (using cv2 to capture/show img ...)
  • python poll_thread_run2.py (using cv2 to run all thread detection based on CPU num)
  • python poll_series_run2.py (using cv2 to run all series detection ...)

2013年9月27日 星期五

fast debug key notes

these are my tips for fast debug.

  • set breakpoint when the assertion was happened
    • like GDB methodology 
      • forward, backward, force signal, release signal
    • tip
      • forcing the error signal value to your expect signal value when the simulation assertion was happened. if the signal was forced, then continuous go through it without rerun again. that can save the interrater running  times
  • dump the error time window waveform without whole simulation time dump
    • tip
      • using the interactive method to dump waveform. 
        • 1. find the error happened time
        • 2. set breakpoint 
        • 3. jumping the previous time window via backward breakpoint
        • 4. open interactive dump waveform command
        • 5. start dumping until the next breakpoint was happened
  • using assertion 
  • using verification IPs
    • sub IP test (selftest)
      • functional test, coverage test, Direct/Random pattern test
    • sub system test (sub system test)
      • protocol test, transaction path test, performance test
    • whole system test (H/S test)
      • OS boot, H/S correlation test

2013年9月14日 星期六

Cadence SimVision UVM/SystemVerilog debugger

transaction level debug via SimVision....

  • transaction waveform info/pin level waveform info 
  • transaction database info
  • UVM phase sequence info
  • assertion info
  • coverage rate
    • functional
    • fsm
    • code
    • assertion
    • performance 
  • debug step by step, like gdb forward, backward, stop point, value dump....
  • unknown signal trace back
  • vif (virtual interface), Driver 




2013年8月21日 星期三

python + systemverilog/verilog + uvm IDE (vim)



  • %vim command line to source the uvm syntax
    • : source ~/.vim/syntax/verilog_systemverilog.vim
  • project:
    • https://github.com/funningboy/vim
  • ref:
    • http://blog.eddie.com.tw/
    • https://github.com/kaochenlong/eddie-vim

2013年8月19日 星期一

machine learning note1


  • supervised learning
    • requirement
      • it must have the target/answer in it's training phase
      • using training phase to build up the 
      • using test phase to predict the next value 
    • regression
      • find the next value based on it's regression times, such as the temperature value in tomorrow, stock price in next open time....
      • example

    • classification
      • find the next classification value based on it's regression times, such as the it will rain or not tomorrow?, stock price will go up or down?... 
      • example
        •  
  • non-supervised learning
    • cluster
  • definition
    • http://en.wikipedia.org/wiki/Machine_learninghttp://www.gnu.org/software/octave/

https://class.coursera.org/ml-003/lecture/5
https://sites.google.com/site/octavetech/home

2013年7月14日 星期日

jenkins + python = regression env

Hi all,
this is a python unittest regression flow by jenkins that can help designer daily run testsuites and support the GUI output reports(coverage pass rate)

github:

  • https://github.com/funningboy/ijenkins/blob/master/README
ref:
  • http://jenkins-ci.org/content/python-love-story-virtualenv-and-hudson

2013年5月21日 星期二

deep copy or shadow copy in your systemverilog object

as the same methodology as c/c++ or any languages. we usually used copy function to copy trx to avoid the overwrite trx when the trx had new ptr triggered. this is an sample example about what's the difference between deep copy and shadow copy, in short word. deep copy is top down copy, copy from this(current) level info to it's parents info. shadow copy is template current level copy, only for this level info.
class Based #(type T=int unsigned);
  T val;

  function new (T v=0);
    val = v; // assign new val
  endfunction : new

  virtual function void deep_copy(Based b);
    assert(b!=null);
    b.val = val; // b.val = this.val
  endfunction : deep_copy

  virtual function void shadow_copy(Based b);
    assert(b!=null);
    b.val = val; // b.val = this.val
  endfunction : shadow_copy

  virtual function bool eq(Based b);
    return b.val == val;
  endfunction : eq

endclass : Based

class A #(type T=int unsigned) extens Based;
  T val_a

  function new (T v=0);
    super.new();
    val_a = v; // assign val_a
  endfunction : new 

  virtual function void deep_copy(A a); 
    assert(a!=null);
    Based b;
    a.val_a = val_a;
    $cast(b,a);
    super.deep_copy(b);
    // or
    // a.val_a = val_a
    // a.val  = super.val
  endfunction : deep_copy

  // operator overwrite ... eq, lt, lt, ...
  virtual function bool eq(A a0);
    assert(a0!=null);
    Based b0;
    $cast(b0,a0);
    return val_a == a0.val_a & super.eq(b0);
  endfunction : eq


endclass : A


A a0 = new(1);
A a1 = new(2);

a0.val_a = 3;
a0.val = 2;

a0.deep_copy(a1);

// check a0, a1 contains are eq  a0 = a1
assert(a0.eq(a1));  

waveform modeling

as well as your are a ATE engineer, you may very familiar with the ATE test pattern formats that can transfer the waveform info into sample digital codes.
this is  a very example code for req/grant test case.
// timing modeling
task req_grant_00();                                                                                                                                                                 
  m_vif.REQ   <= 0;
  m_vif.GRANT <= 0;
  @(posedge m_vif.CLK);
endtask : req_grant_00

task req_grant_01();
  m_vif.REQ   <= 0;
  m_vif.GRANT <= 1;
  @(posedge m_vif.CLK);
endtask : req_grant_01

task req_grant_10();
  m_vif.REQ   <= 1;
  m_vif.GRANT <= 0;
  @(posedge m_vif.CLK);
endtask : req_grant_10

task req_grant_11();
  m_vif.REQ   <= 1;
  m_vif.GRANT <= 1;
  @(posedge m_vif.CLK);
endtask : req_grant_1

task

task wave_gen();
  list = {`ON_OFF, `ON_ON, `OFF_ON, `OFF_OFF};

  foreach(list[i]) begin
    case(list[i])
      `ON_OFF : req_grant_10();
      `ON_ON  : req_grant_11();
      `OFF_OFF: req_grant_00();
      `OFF_ON : req_grant_01();
    endcase
  end 
endtask

2013年5月17日 星期五

UVM scoreboard to check with c/c++ golden model via uvm analysis port

1.systemverilog DPI interface to interconnect the c/c++ part and systemverilog part

2.uvm analysis port to valid event channel
// golden cehck via uvm analysis port
// ps : the port should be connected to it's callback module. that uvm can collected.
// ex: item_port.connect( analysis_export );

uvm_analysis_port item_port

// DPI import ... for our golen model
import "DPI" void *yuv2rgb(int unsigned y, int unsigned u, int unsigned v);  
// yub2rgb(void* trx); using ptr is a more friendly interface....
import "DPI" void *rgb2yuv(int unsigned r, int unsigned g, int unsigned b); 

// callback func called from callable func/module
task callback(sample_trx trx);

  assert(trx!=null);
  if (trx.type == YUV2RGB)
    dpi_c_yuv2rgb(trx);
  else
    dpi_c_rgb2yuv(trx);

endtask

void dpi_c_yuv2rgb(sample_trx trx);
                                                                                                                                                                                    
  assert(trx!=null);
  c_rst = yuv2rgb(trx.y, trx.u, trx.v)
  assert( c_rst.r == trx.r &
          c_rst.g == trx.g &
          c_rst.b == trx.b);
endtask

2013年5月16日 星期四

adding performance monitor to your design

the UVM monitor can play not only a functional checker but also a performance checker which means, user can use it more quickly to find out where is their design bottleneck without waveform tracing. in this topic, we focused on how to use UVM monitor to point out the collected transactions had timing violation immediately when the simulation was running.

we write a UVM SystemVerilog "req happened until grant received" to our demo case.

 
// spawn sub procs(threads)                                                                                                       
task run_phase(uvm_phase);
  fork
    sent_req();
    sent_grant();

    collected_req();
    collected_grant();

    check_performance();
    check_protocol();
  join
endtask : run_phase


// sent req 
task sent_req();

  forever begin
    // random  wait ....
    repeat($urandom_range(8,16)) @(posedge m_vif.CLK);

    // sent req 
    `delay(conf.half_cycle);
    m_vif.REQ <= `TRUE;
    @(posedge m_vif.CLK);

    // wait until grant received
    while(!m_vif.GRANT) @(posedge m_vif.CLK);

    // free req 
    `delay(conf.half_cycle);
    m_vif.REQ <= `FALSE;
    @(posedge m_vif.CLK);

  end

endtask : sent_req


// snet grant
task sent grant();

  forever begin

    // sent unvalid grant
    `delay(conf.half_cycle);
    m_vif.GRANT <= `FALSE;
    @(posedge m_vif.CLK);

    // wait until req received
    while(!m_vif.REQ) @(posedge m_vif.CLK);

    // random wait ...
    repeat($urandom_range(8,16)) @(posedge m_vif.CLK);

    // sent valid grant to free req
    `delay(conf.half_cycle);
    m_vif.GRANT <= `TRUE;
    @(posedge m_vif.CLK);

  end

endtask : sent grant                                                                                                              


task collected_req();

  forever begin
     // @ neg edge check
      @(negedge m_vif.CLK iff m_vif.REQ);

      // assert only one fifo deep when req/grant case
      assert(m_trx_q.size() < 1);

      // collect trx
      TRX m_trx = new();
      m_trx.REQ = m_vif.REQ;
      m_trx.TIME = $time;
      m_trx_q.push_back(m_trx);

  end
endtask : collected_req


task collected_grant();

  forever begin
    // @ neg edge cehck
    @(negedge m_vif.CLK iff m_vif.GRANT);

    //assert the queue size must be 1, means the req has been stored in the queue
    assert(m_trx.q.size() == 1);

    // free queue
    m_trx_q.pop_front();

  end
                                                                                                                                  
endtask : collected_grant


task check_performance();
  forever begin
    // at each pos edge check
    @(posedge m_vif.CLK);

    //assert queue
    if (m_trx_q.size() == 1) begin
        if ($time - m_trx_q[0].TIME > conf.min_offset) begin
          `uvm_error(get_full_name(), {$psprintf("out of time %d"), conf.min_offset}, UVM_LOW)
        end else begin
          `uvm_error(get_full_name(), {$psprintf("req/grant seuence is not valid")}, UVM_LOW)
        end
    end
  end

endtask             

2013年5月15日 星期三

python unittest + UVM testsuites + Jenkins = DUT regression

in recently, i got a order from my boss. he asked me to build up a automatically unittest env that can very quick to know where is the problem such as protocol error, functional error, timing error ... when the design is changed. the below list is my auto regression flow and requirements


  • i used python unittest to our based unittest framework
    • python unittest
      • check testsuite is pass/fail
    • python nose 
      • call python unittest folder and testsuites
    • python subprocess/multiprocess
      • call system call (irun, vcs....)
    • python re(regular expression)
      • check simulation result is pass/faill if the error tokens are not found

  • UVM testsuites
    • define UVM test sequence for your simulator
      • irun -uvm +UVM_TESTNAME=""...
    • prepare your test sequence
      • like xxSequences.sv
        • test_1read_after_1write
        • test_mread_after_mwrite
        • test_read_write_at_same_time
  • jenkins
    • job manager
      • daily regression run 

2013年5月8日 星期三

Microsemi BFM script language


  • a very useful script language for bus performance estimation and bus functional check
    • example:
      • # read B uart 0;
        Reading offset 0 of uart – data = 0x1c
        # write B uart 4 bb;
        Writing 0xbb to offset 4 of uart
        # read B uart 8;
        Reading offset 8 of uart – data = 0x28
        # write B mac 30 11;
        Writing 0x11 to offset 30 of mac
        # readcheck B mac 11;
        Reading offset 0 of mac
        Error: Expected data = 0x11, Actual data = 0x22
        Test Failed, with 1 error
          
          

      • 
        
      • advantage
        • simple 
        • error check 
      • disadvantage
        • no time stamp
          • maybe it use ASAP(as soon as possible) methodology to transfer transactions, it means masters or slaves are not in busy status, or fetch/push buffers not full
        • no atomic transfer
          • if valid/ready is not continuous in the burst transaction, the interlevel transactions will happened, 
          • like A1(4), A2(4), A1 has burst 4 trxs, A2 has burst 4 trxs.
            • A1(2), A2(2), A1(2), A2(2) => atomic transactions when the A1 or A2 has busy or error in the internal transaction.

    2013年5月1日 星期三

    AXI BFM(bus function model)


    • standard protocol
      • write phase (fork events)
        • write address phase
          • collect transactions when AXI_AWVALID and AXI_AWREADY
        • write data phase
          • collect transactions when AXI_WVALID and AXI_WREADY
        • write response phase
          • collect transactions when AXI_BVALID and AXI_BREADY
        • the valid transaction should have the same ID at address, data, response 

      • read phase(fork events)
        • read address phase
          • collect transactions when AXI_ARVALID and AXI_ARREADY
        • read data phase
          • collect transactions when AXI_RVALID and AXI_RREADY
        • the valid transaction should have the same ID at address, data
    • extend protocol
      • qos
      • user
      • region
      • lock
      • cache
      • strb
    • https://github.com/funningboy/axi-bfm

    2013年4月14日 星期日

    UVM systemverilog assertion(SVA)


    • assertion
      • assert in C/C++, pointer check 
        • A *a = new A();
        • assert(a!=NULL);
        • a->do_some_thing()...
      • main purpose
        • performance hazards
          • performance requirement throughput for real time issue
        • wrong functionality
          • functional error when the transaction is miss-match for each condition description
          • Assertion active at both clock edges
            • a2: assert property(@(posedge clk)a|->b[*8]); 
          • Sequence used as clocking event 
            • sequence s;
              @(posedge clk) a[*5];

              endsequence
              a3: assert property (@(s) b |-> ##3 c); 
          • Complex Boolean expression used for clock 
            • a5: assert property (@(clk iff en) p1);    
          • Wrong argument type or size
            • `ASSERTS_ONE_HOT(a7, {sig1, sig2, sig3} ...);    
          • short circuit 
            • function bit legal_state(
            • bit [0:3] current, bit valid);
            • a12: assert #0 (valid |-> current != '0);
            • legal_state = valid && $onehot(current);
            • endfunction
            • …
            • if (status || legal_state(valid, state)) 
            •   
          • Action block without functional call
            • `define MY_MUTEX(sig) \
            • assert #0($onehot0(sig))
            • always @(posedge clk) begin
            • ...
            • `MY_MUTEX(fsm_1_state)
            • `MY_MUTEX(fsm_2_state); 
            • end
          • req/grant protocol check
            • a14: assert property
            • (@clk req |-> strong(##[1:$] gnt));
          • assertion for coverage
            • c16: cover property (@clk 
            • (state==REQ)##1 (state==SEND));
          •  possibly ignored assertions
          • low coverage(pattern valid/invalid, critical case, how to inc the coverage value)



    2013年3月1日 星期五

    ECO tool for NetList Verilog

    hi all,

    if your are a CAD Engineer in IC design house, i think you always take a lot of time to do recourse jobs... like reassign wire names, add new cells, check netlist...that's really suck things. why not try this tool that can help you insert ECO cell automatically, and double check the ECO cell inserted is ok when you running this script.

    features
    1. ECO cell insert
    2. ECO cell check
    3. Module output Fanin check
    4. Module input Fanout check
    5. cell, port, net, width check

    more to do
    1. support Graph alg(NetworkX)
    2. support assign statement
    3. support STA, Timing check
    4. support simulation???

    Example:
    Definition about input/output, ECO file...

    # our org NetList file
            vtest = \
    """
    module TOP( in, out );
    input [1:0] in;
    output [1:0] out;
    INVD1 U0( .I( in[0] ), .ZN( out[0] ) );
    INVD1 U1( .I( in[1] ), .ZN( out[1] ) );
    endmodule
    """
    
    # our cell lib file
            ytest = \
    """
    AN2D1:
      inputs:
        A1: 1
        A2: 1
      outputs:
        Z: 1
      primitive: A1 and A2
    
    INVD1:
      inputs:
        I: 1
      outputs:
        ZN: 1
      primitive: not I
    """
    
    # our ECO file description, define where is the Input, Output link coming from, and it's assign value
            etest = \
    """
    AN2D1:
      inputs:
        A1: new_in
        A2: in[0]
      outputs:
        Z:  new_out
      primitive: A1 and A2
    """
    
    # our expect value
            exptest = \
    """
    module TOP( new_in, new_out, in, out );
    
        output [  1: 0 ] out;
        input  [  1: 0 ] in;
        input new_in;
        output new_out;
    
        AN2D1 ECO_AN2D1( .A1( new_in ), .A2( in[0]), .Z( new_out ) );
        INVD1 U0( .I( in[0] ), .ZN( out[0] ) );
        INVD1 U1( .I( in[1] ), .ZN( out[1] ) );
    endmodule                                                                                                                                                                            
    """
    
    

    How to run
        Add new ECO cell in org NetList file.
        >>> eco = ECO()                                                                                                                                                                  
        >>> eco.readYAML("test/gates.yml") # read cell libs
        >>> eco.readVerilog("test/Iface_test.gv") # read org verilog Netlist file
        >>> eco.link("Iface_test") # link top module
        >>> eco.checkDesign() # check pre load design is ok
        >>> eco.report()
        >>> eco.readECO("test/ECO.yml") # read eco file
        >>> eco.runECO() # run eco
        >>> eco.checkDesign() # recheck design again when the ECO is done
        >>> eco.report()
        >>> eco.writeVerilog("test/new_Iface_test.gv")
    

    How to run unittest nosetests
    project

    2013年2月18日 星期一

    example MyHDL

    hi all,

    this is a speech about MyHDL in python taipei meeting,
    the free project code can download from git
    thanks


    2013年1月5日 星期六

    vcd file info tracer



    在 IP 驗證時, 除了用 synopsys VIP 來驗證 bus 的 protocol 跟 performance 的分析. 但有時候為了 customer design 時, 會把 protocol 作些變形, 這樣就不符合 standard protocol 的方式. 底下就用大家都熟知的 VCD 擋把 bus info 錄出來轉到 data base 讓使用者可以直接用 query 的方式把 performance 跟 dynamic power 算出來. 底下用 vcdparser.py 把 vcd info 讀出來.之後再透過後端的 big data 處理把資料寫到 data base 上.
    python db link
    """
    conn = sqlite3.connect('example.db')
    c = conn.cursor()
    
    c.execute('''CREATE TABLE vcd
          (version, timeType(s,ns,fs...), time''')
    c.execute('''CREATE TABLE _scopes_
          (scopeDomain, scopeType(fork,module,...), top(scopeNm)''')
    c.execute('''CREATE TABLE _signals_
          (scopeDomain, signalID, signalType(Real,Bit,...), width, name''')
    c.execute('''CREATE TABLE _signalID_ # _0_
                 (time , val)''')
    
    # ex :
    #
    # module top();
    # #0 clk =1;
    # #5 clk =0; ...
    # endmodule
    
    # header create
    c.execute('''CREATE TABLE _scopes_
          (scopeDomain, scopeType, scopeNm''')
    c.execute('''CREATE TABLE _signals_
          (scopeDomain, signalID, signalType, width, name''')
    c.execute('''CREATE TABLE _signalID_ # _0_
                 (time , val)''')
    
    # body create
    c.execute("INSERT INTO _scopes_ VALUES (0, 1(module), "top")")
    c.execute("INSERT INTO _signals_ VALUES (0, 0, 0(bit), "top.clk")")
    
    c.execute("INSERT INTO _0_ VALUES (0, 1)")
    c.execute("INSERT INTO _1_ VALUES (5, 0)")
    
    #
    conn.commit()
    c.close()
    """
    
    VcdParser.py
    from __future__ import with_statement
    from itertools import dropwhile, takewhile, izip
    from collections import defaultdict
    from pprint import pprint as pp
    
    from os import *
    import io
    from src.vcdDB  import *
    from src.vcdErr import *
    from src.vcdContext import *
    
    
    class VcdParser(object):
      """ parser VCD 2 VcdDB """
    
      def __init__(self,vcd=None):
        self._vfile = None
    
        try:
          if not isinstance(vcd,VcdDB):
           raise VcdParserError("vcdDB ptr is None")
        except VcdDBError, e:
          print e._msg
    
        self._vcd   = vcd
    
    
      def parse_error(self,tokeniser, keyword):
        raise "Don't understand keyword: " + keyword
    
    
      def do_drop_declaration(self,tokeniser, keyword):
        dropwhile(lambda x: x != "$end", tokeniser).next()
    
    
      def do_vcd_date(self,tokeniser, keyword):
        """ parser vcd date and set 2 VcdDB::date """
    
        date = ' '.join(takewhile(lambda x: x != "$end", tokeniser))
        self._vcd.set_date(date)
    
    
      def do_vcd_timescale(self,tokeniser, keyword):
        """ parser vcd timescale and set 2 VcdDB::timescale """
    
        val, scale = tuple(takewhile(lambda x: x!= "$end", tokeniser))
        self._vcd.set_timescale(scale,val)
    
    
      def do_vcd_version(self,tokeniser, keyword):
        """ parser vcd version and set 2 VcdDB::version """
    
        version = ' '.join(takewhile(lambda x: x!= "$end", tokeniser))
        self._vcd.set_version(version)
    
    
      def do_vcd_enddefinitions(self,tokeniser, keyword):
        """ parser vcd enddefinitions """
    
        self.do_drop_declaration(tokeniser, keyword)
        self._vcd.set_enddefinition(1)
    
    
      def do_vcd_scope(self,tokeniser, keyword):
        """ parser vcd scope and set 2 VcdDB::scope """
    
        scope, name = tuple(takewhile(lambda x: x != "$end", tokeniser))
        self._vcd.set_scope(self._vcd,scope,name)
    
    
      def do_vcd_upscope(self,tokeniser, keyword):
        """ parser vcd upscope """
    
        tokeniser.next()
    
    
      def do_vcd_var(self,tokeniser, keyword):
        """ parser vcd signalInfo and set 2 vcdDB::nameMap """
    
        varTyp, width, uniqNm, refNm = tuple(takewhile(lambda x: x != "$end", tokeniser))
        scope = self._vcd.get_end_scope()
        maptb = self._vcd.get_mapTb()
    
        scope.set_signals(scope,varTyp,refNm,width)
        signal = scope.get_signal(refNm)
        maptb.set_tb(uniqNm,signal)
    
    
      def do_vcd_dumpall(tokeniser, keyword): pass
      def do_vcd_dumpoff(tokeniser, keyword): pass
      def do_vcd_dumpon(tokeniser, keyword): pass
      def do_vcd_dumpvars(tokeniser, keyword): pass
      def do_vcd_end(tokeniser, keyword): pass
    
    
      def vcd_2_VcdDB(self,vcdfile=None):
        """ parser vcd file 2 VcdDB format """
    
      # define key 2 proc
        keyword2handler = {
            # declaration_keyword ::=
            "$comment":        self.do_drop_declaration,
            "$date":           self.do_vcd_date,
            "$enddefinitions": self.do_vcd_enddefinitions,
            "$scope":          self.do_vcd_scope,
            "$timescale":      self.do_vcd_timescale,
            "$upscope":        self.do_vcd_upscope,
            "$var":            self.do_vcd_var,
            "$version":        self.do_vcd_version,
            # simulation_keyword ::=
            "$dumpall":        self.do_vcd_dumpall,
            "$dumpoff":        self.do_vcd_dumpoff,
            "$dumpon":         self.do_vcd_dumpon,
            "$dumpvars":       self.do_vcd_dumpvars,
            "$end":            self.do_vcd_end,
            }
    
        keyword2handler = defaultdict(self.parse_error, keyword2handler)
    
        f = io.open(vcdfile,"r")
        tokeniser = (word for line in f for word in line.split() if word)
        time = 0
        for count,token in enumerate(tokeniser):
          if self._vcd.get_enddefinition() != 1:
            keyword2handler[token](tokeniser, token)
          else:
            c, rest = token[0], token[1:]
            if c == '$':
              # skip $dump* tokens and $end tokens in sim section
              continue
            # time info
            elif c == '#':
              time = rest
            # (1)bit info
            elif c in '01xXzZ':
              uniqNm = rest
              val    = c
              maptb  = self._vcd.get_mapTb()
         signal = maptb.get_tb(uniqNm)
              signal.set_NodeInfoList(signal,time,"bit",val)
            # binary info
            elif c in 'bB':
       uniqNm = tokeniser.next()
       val    = rest
       maptb  = self._vcd.get_mapTb()
       signal = maptb.get_tb(uniqNm)
       signal.set_NodeInfoList(signal,time,"binary",val)
            # real info
            elif c in 'rR':
       uniqNm = tokeniser.next()
       val    = rest
       maptb  = self._vcd.get_mapTb()
       signal = maptb.get_tb(uniqNm)
       signal.set_NodeInfoList(signal,time,"real",val)
            else:
              raise "Don't understand: %s After %i words" % (token, count)
    
        f.close()
    
        return self._vcd
    
    
    code download 主要改寫 writing-vcd-to-toggle-count-generator 成我們要跟底層溝通的api




    Refs:
    http://www.semiwiki.com/forum/content/753-what-changes-expect-verification-ip-landscape-after-synopsys-acquisition-nsys.html
    VMM performance user guide
    http://vmmcentral.org/pdfs/perf_user_guide.pdf
    http://i.cmpnet.com/eetimes/news/online/2010/09/Whitepaper_Mediatek_2010.pdf


    2011年8月21日 星期日

    BDD (Binary decision diagram)

    binary decision tree.以前唸書的時候,邏輯設計課要學卡諾圖(Karnaugh map)化簡,不過現在有一個比較好用的tool,BDD(binary decision diagram)可以幫我們判斷出條件 Path 的路徑 跟 Output 的 case 解.當然這也可以分析出 code 的 condition coverage 跟做些 reduction 的 methods. 可參考底下的教學跟安裝. Refs: http://en.wikipedia.org/wiki/Binary_decision_diagram http://lyle.smu.edu/~bxu/SimpleADD.html

    2011年8月3日 星期三

    sample simulation env

    底下寫了個 pseudo code for sample simulation.主要建立起每個 Signal 的 class. 在依序填入 Signallist 中,之後根據現在的 time cycle 取得 runnable 的 Signal, 取得 Signal 後,根據其 Driver 的 Method 做動作.如果其 Method 會 Driver 到其他的 input/inout Signal, 再把其 Driver 的 Signal 填入 Signallist 中,再重新 Sort 一次,直到這次的 Cycle 內的所有 Signals 都以完成.
    # Sample.v
    # module Sample(clk,rst,a,c)
    # input  clk,rst;
    # intput a[31:0];
    # output c[31:0];
    # reg    b[31:0];
    #
    # assign c = (b==10)? b+a : a;
    #
    # always@ (posedge clk or posedge rst) begin
    # if (rst==1'b1)
    #     b <= 0;
    #  else
    #     b <= b + 1;
    # end
    # endmodule
    #
    # test_Sample.v
    # always
    # #10 clk ~= clk  
    #
    # initial begin
    # #0  Rst = 1'b0;
    # #5  Rst = 1'b1;
    # #20 Rst = 1'b0; 
    # .... 
    # #100 $finish 
    # end
    #
    
    init_Architecture() {
     _module_      = Module({name:Sample});
     
     _a_           = _module_.Input.Signal([{name:a},
                                            {length:32},
                                            {cur:[{time:0},{val:x}]},
                                            {nxt:[{time:0},{val:x}]}]);
    
     _c_           = _module_.Output.Signal([{name:c},
                                             {length:32},
                                             {cur:[{time:0},{val:x}]},
                                             {nxt:[{time:0},{val:x}]}]); 
    
     _clk_         = _module_.Clk.Signal([{name:Clk},
                                          {length:1},
                                          {cur:[{time:0},{val:x}]},
                                          {nxt:[{time:0},{val:x}]}]});
        
     _rst_         = _module_.Rst.Signal(...); 
    
     _b_           = _module_.Reg.Signal(...);
    
     _method_0_    = _module_.Method([{{C1:{_rst_==1'b1}},{P1:{_b_=0}}},
                                      {{C2:{_rst_==1'b0}},{P2:{_b_=_b_+1}}}]);
    
     [_clk_,_rst_].set_Driver(_method_0_);
    
     _method_1_    = _module_.Method([{{C1:{_b_==10}},{P1:{c=b+a}}},
                                      {{C2:{_b_!=10}},{P2:{c=a}}}]);
    
     [_b_].set_Driver(_method_1_);
       
     [_clk_,_rst_,_a_,_c_,_b_].set_Parent(_module_);
     [_method_0_,_method_1_].set_Parent(_module_); 
    
     gl_Module_List.push(_module_);
    
     _module_.Signal_List.push([_a_,_c_,_clk_,_rst_]);
    }
    
    
    
    init_Time_Wave(){
    
     _gl_clk_  = Clk([{start_time:0},
                      {end_time:100},
                      {period:10}]);
    
     _gl_rst_  = Rst([{time:  0:F},
                      {time:  5:R},
                      {time: 20:F},
                      {time: 80:R},
                      {time:100:F}]);
    
     _gl_time_ = Time();
    }
    
    
    
    
    run_gl_Module_List(time cur_time,
                time nxt_time) {
    
     schedule_list = [];
     update_list   = [];
    
     # @ find the signals
     foreach _module_ ( gl_Module_List ){
    
       foreach _signal_ ( _module_.Signal_List )
           if( _signal_.cur.time <= cur_time )
               schedule_list.push(_signal_);   
              
     }
    
     schedule_list.sort_by_time();
    
    
     while( !schedule_list.empty() ){
    
         _schedule_ = schedule_list.pop_left();
         _driver_   = _schedule_.get_Driver();
    
         method_list = _driver_.get_Methods();
      
         foreach _method_ ( method_list )
             update_list = method.run_Signal_update();
                    
    
         foreach _update_ ( update_list ){
    
          Signal(_update_).cur.val = Signal(_update_).nxt.val;
          Signal(_update_).cur.time = nxt_time;
          Signal(_update_).nxt_time = nxt_time + nxt_time - cur_time;
    
            if( Signal(_update_).get_Driver()!= Output ){
                schedule_list.push(_update_);
                schedule_list.sort_by_time();
            }
    
         }
     }
    }
    
    
    
    run_Simulation(){
    
     _gl_cur_time_ = _gl_clk_.start_time();
     _gl_nxt_time_ = 0;
     
     # check simulation time
     while ( _gl_cur_time <= _gl_clk.end_time() ) {
    
       _gl_nxt_time = _gl_cur_time_ + _gl_clk_.period()>>1; # @ posedge/negedge edge check
     
       run_gl_Module_List(_gl_cur_time_,_gl_nxt_time_); 
    
       _gl_cur_time = _gl_nxt_time;
    
     }
    }
    
    refs: http://www.ocpip.org/datasheets.php http://www.greensocs.com/ source code download http://sourceforge.net/projects/greensocs/develop