xbus UVM example

purpose

a sample bus UVM/SV verification env that contains direct pattern, random pattern, trx replay pattern

pattern definition

1. direct pattern : normal read/write test, like read after write test, the expected and answer had already known
2. random pattern : random test based on it's constrain rule set
3. trx replay pattern : replay trx via DPI interface supported

how to run it?

1.you can check our testsuites first, we provide three kinds of test at path ./sv/pat

1.1. for direct pattern +UVM_TESTNAME=test_xbus_normal_rw_seq_lib

1.2. for random pattern +UVM_TESTNAME=test_xbus_random_rw_seq_lib

1.3. for trx replay pattern +UVM_TESTNAME=test_xbus_adaptor_seq_lib

2.setup irun env please make sure your irun version is > 12.x

3.% irun -f run.f

https://github.com/funningboy/xbus

fast debug key notes

these are my tips for fast debug.

• set breakpoint when the assertion was happened
• like GDB methodology 
• forward, backward, force signal, release signal
• tip
• forcing the error signal value to your expect signal value when the simulation assertion was happened. if the signal was forced, then continuous go through it without rerun again. that can save the interrater running  times
  
• dump the error time window waveform without whole simulation time dump
• tip
• using the interactive method to dump waveform. 
• 1. find the error happened time
• 2. set breakpoint 
• 3. jumping the previous time window via backward breakpoint
• 4. open interactive dump waveform command
• 5. start dumping until the next breakpoint was happened
  
• using assertion 
• using verification IPs
• sub IP test (selftest)
• functional test, coverage test, Direct/Random pattern test
• sub system test (sub system test)
• protocol test, transaction path test, performance test
• whole system test (H/S test)
• OS boot, H/S correlation test

coverage group based on different bins

bus interface coverage catagology

classification

• functional coverage bins
• address rage bins
• burst len bins
• read/write bins
• burst type bins
• byten enable bins
• cross coverage 
• read trx
• address, burst, read, ....
• write trx
• address, burst, write, ....
• performance coverage bins
• standard/normal bins
• out standard bins
• below standard bins
• cross coverage
• read trx
• standard
• write trx
• standard
• toggle coverage bins
• 0 -> 1 
• 1 -> 0
• cross coverage
• read trx
• 0 -> 1 -> 0
• write trx
• 0 -> 1 -> 0
• FSM coverage bins
• default pass
• protocol coverage bins
• atomic bins
• out of order bins
• divide/conquer bins
• address mapping table bins span tree
• hit rate bins (cache coherence)
• 
  

Cadence SimVision UVM/SystemVerilog debugger

transaction level debug via SimVision....

• transaction waveform info/pin level waveform info 
• transaction database info
• UVM phase sequence info
• assertion info
• coverage rate
• functional
• fsm
• code
• assertion
• performance 
• debug step by step, like gdb forward, backward, stop point, value dump....
• unknown signal trace back
• vif (virtual interface), Driver