xbus UVM example

purpose

a sample bus UVM/SV verification env that contains direct pattern, random pattern, trx replay pattern

pattern definition

1. direct pattern : normal read/write test, like read after write test, the expected and answer had already known
2. random pattern : random test based on it's constrain rule set
3. trx replay pattern : replay trx via DPI interface supported

how to run it?

1.you can check our testsuites first, we provide three kinds of test at path ./sv/pat

1.1. for direct pattern +UVM_TESTNAME=test_xbus_normal_rw_seq_lib

1.2. for random pattern +UVM_TESTNAME=test_xbus_random_rw_seq_lib

1.3. for trx replay pattern +UVM_TESTNAME=test_xbus_adaptor_seq_lib

2.setup irun env please make sure your irun version is > 12.x

3.% irun -f run.f

https://github.com/funningboy/xbus

Demo for interview

最近為了 interview 寫了幾個小 project. 有興趣的就參考看看吧！！

UVM AXI BFM 1.0 release

supported list

• AXI3/AXI4 bus protocol
• out of order/ inorder transactions
• each write/read phase is independent
• addr/write/resp is independent
• interlevel
• split
• performance watch dog 
• protocol watch dog
• performance report
• MAX, AVG, MIN bus bandwidth
• through put
• transaction list(disassemble bus info)
•  virtual master
• define each phase delay(req to grant or each valid/ready) or drive trx out time stamp
• virtual slave
• define each phase delay(req to grant or each valid/ready) or drive trx out time stamp
• scoreboard
• check connection
• check the memory read write is pass when the read/write trx in the same address, the read trx must be finished first than write trx to avoid the overwrite the address issue.
• STL 
• user define TRX language
• SystemC analysis port 
• user can use analysis port to link third part debug model by using DPI interface like Verilog to SystemC  or Verilog to C/C++
• 
  
• https://github.com/funningboy/uvm_axi

Xilinx ucf constrain notes

ucf constrain

• timing constrain
• input pad to first flip-flop groups
• input offset
• internal flip-flop to flip flop groups
• period
• out flip-flop to output pad groups 
• output offset
• clock
• offset
• duty
• jitter
• rotate
• 90 
• 180
• 270
• multi cycle path
• from one clock dom to another clock dom
• using async fifo to avoid the data missing issue
• data valid
• req fifo.empty/fifo.full
• status
• false path
• not normal paths
• -to
• -from -to
• -through
• -from -through -to 
• data path
• normal paths
• fanout
• set maxfanout
• DCM / DLL/ PLL
• ECO div/mux
• TNM (timing group)
• 
  
• pin assignment constrain
• pad assignment 
• 
  
• slack
• Slack (setup path): =  (requirement - (data path - clock path 
• skew + uncertainty))
• Slack (hold path): = requirement - (clock path skew + uncertainty - data path) 

deep copy or shadow copy in your systemverilog object

as the same methodology as c/c++ or any languages. we usually used copy function to copy trx to avoid the overwrite trx when the trx had new ptr triggered. this is an sample example about what's the difference between deep copy and shadow copy, in short word. deep copy is top down copy, copy from this(current) level info to it's parents info. shadow copy is template current level copy, only for this level info.

class Based #(type T=int unsigned);
  T val;

  function new (T v=0);
    val = v; // assign new val
  endfunction : new

  virtual function void deep_copy(Based b);
    assert(b!=null);
    b.val = val; // b.val = this.val
  endfunction : deep_copy

  virtual function void shadow_copy(Based b);
    assert(b!=null);
    b.val = val; // b.val = this.val
  endfunction : shadow_copy

  virtual function bool eq(Based b);
    return b.val == val;
  endfunction : eq

endclass : Based

class A #(type T=int unsigned) extens Based;
  T val_a

  function new (T v=0);
    super.new();
    val_a = v; // assign val_a
  endfunction : new 

  virtual function void deep_copy(A a); 
    assert(a!=null);
    Based b;
    a.val_a = val_a;
    $cast(b,a);
    super.deep_copy(b);
    // or
    // a.val_a = val_a
    // a.val  = super.val
  endfunction : deep_copy

  // operator overwrite ... eq, lt, lt, ...
  virtual function bool eq(A a0);
    assert(a0!=null);
    Based b0;
    $cast(b0,a0);
    return val_a == a0.val_a & super.eq(b0);
  endfunction : eq


endclass : A


A a0 = new(1);
A a1 = new(2);

a0.val_a = 3;
a0.val = 2;

a0.deep_copy(a1);

// check a0, a1 contains are eq  a0 = a1
assert(a0.eq(a1));  

python unittest + UVM testsuites + Jenkins = DUT regression

in recently, i got a order from my boss. he asked me to build up a automatically unittest env that can very quick to know where is the problem such as protocol error, functional error, timing error ... when the design is changed. the below list is my auto regression flow and requirements

• i used python unittest to our based unittest framework
• python unittest
• check testsuite is pass/fail
• python nose 
• call python unittest folder and testsuites
• python subprocess/multiprocess
• call system call (irun, vcs....)
• python re(regular expression)
• check simulation result is pass/faill if the error tokens are not found
• 
  
• UVM testsuites
• define UVM test sequence for your simulator
• irun -uvm +UVM_TESTNAME=""...
• prepare your test sequence
• like xxSequences.sv
• test_1read_after_1write
• test_mread_after_mwrite
• test_read_write_at_same_time
• jenkins
• job manager
• daily regression run 

synplify + ise TCL xflow

http://outputlogic.com/xcell_using_xilinx_tools/74_xperts_04.pdf https://github.com/dlitz/openmsp430/blob/master/core/synthesis/actel/synplify.tcl https://github.com/martinjthompson/VHDL-compare/blob/master/Synplify/rev_1/run_ise.tcl https://github.com/martinjthompson/VHDL-compare/tree/master/Synplify https://github.com/zakiali/pocket_corr/blob/master/pfb_core/SgIseProject.tcl

SystemVerilog Unit test = SVUnit = TDD(test drivent Development of Verification IP)

SystemVerilog UVM Unit test framework

• Methodology
• get UVM domain class and register it to unit test list
• fetch runnable  test suite from test list, the sorted priority is based on schedule manager definition
• collect test suite UVM report 
• report pass/fail coverages

ex:

 
  //************************************************************
  // Test:
  //   xformation_test
  //  
  // Desc:
  //   ensure that objects going through the simple model have                                                                                                                       
  //   their field property updated appropriately (multiply by
  //   2)
  //************************************************************
  `SVTEST(xformation_test)
    begin
      simple_xaction in_tr = new();
      simple_xaction out_tr;
 
      void'(in_tr.randomize() with { field == 2; }); 
 
      put_port.put(in_tr);
      get_port.get(out_tr);
 
      `FAIL_IF(in_tr.field != 2); 
      `FAIL_IF(out_tr.field != 4); 
    end 
  `SVTEST_END(xformation_test)

ref : http://www.agilesoc.com/svunit/

SystemVerilog parallel tasks by event trigger

SystemVeilog event trigger is implemented by event manager, that can define the dependences of parent and child tasks. and each tasks will be registered in event list when the building phase is done, after it, the task manager will sort event list by it's dependence or timing (such as E(timing(0)(0)), E(timing(1)(1)) E0 > E1, E0 will be run first than E1.

AXI write phase example. using delay constrain to define which one is first, which one is second

// @ write phase before write addr phase
// cfg.write_addr_delay = 10;
// cdg.write_data_phase = 0;


// @ write phase after write addr phase
// cfg.write_addr_phase = 0;
// cfg.write_data_phase = 10;

task run_phase();
  fork
    write_addr_phase();
    write_data_phase();
    get_next_trx();
  join
endtask


task get_next_trx();
  forever begin
    @(posedge vif.clk);
    if (sequencer.item.has_next_trx()) begin
      trx = sequencer.item.get_next_trx();
      if (trx.rw == `WRITE)
        -> start_write;
      else
        -> start_read;
    end 
  end 
endtask

task write_addr_phase();
  forever begin
    if (start_write.triggered) begin
      repeat(cfg.write_addr_delay) @(posedge vif.clk);
      // do write phase
    end 
  end 
endtask

task write_data_phase();
  forever begin
    if (start_write.triggered) begin
      repeat(cfg.write_data_delay) @(posedge vif.clk);
      // do data phase
  end 
endtask

PyHVL = verilog PLI is going died....

• open source tool supported 
• iverilog VPI 2.0 
• http://iverilog.wikia.com/wiki/Using_VPI
• what's VPI/PLI(Verilog Procedural Interface)
• http://en.wikipedia.org/wiki/Verilog_Procedural_Interface
• what's DPI(SystemVerilog Direct Programming Interface)
• http://en.wikipedia.org/wiki/SystemVerilog_DPI
• third party language support 
• perl
• http://www.veripool.org/wiki/verilog-pli/Manual-verilog-pli
• ruby
• http://snk.tuxfamily.org/lib/ruby-vpi/
• python
• http://sourceforge.net/projects/pyhvl/?source=dlp
• disadvantage
• hard to read
• more rules need to follow
• init pli
• register pli 
• free pli
• using third part language to mix simulation run that's very difficult for designer view. they need to know how to driver system call and catch the simulation error when the segment fault happened 
• c 
• only for behavior model verification / profile
• why not using SystemVerilog + DPI to replace it?
• more closer with Verilog language
• more easily to understand 
• OO suport
• more flexible to designer(customer DPI)
• UVM 

AXI BFM(bus function model)

• standard protocol
• write phase (fork events)
• write address phase
• collect transactions when AXI_AWVALID and AXI_AWREADY
• write data phase
• collect transactions when AXI_WVALID and AXI_WREADY
• write response phase
• collect transactions when AXI_BVALID and AXI_BREADY
• the valid transaction should have the same ID at address, data, response 
• 
  
• read phase(fork events)
• read address phase
• collect transactions when AXI_ARVALID and AXI_ARREADY
• read data phase
• collect transactions when AXI_RVALID and AXI_RREADY
• the valid transaction should have the same ID at address, data
• extend protocol
• qos
• user
• region
• lock
• cache
• strb
• https://github.com/funningboy/axi-bfm

UVM guide line

• Naming rule
• axi_package, axi_monitor.svh
• how to debug
• if (debug) `uvm_info("DEBUG", msg, UVM_MEDIUM)
• uvm_factory  factory = uvm_factory.get(); factory.print();
• uvm_top.print_topology()
• how to trace connection 
• use "get_connect_to()", "get_provide_to()", children[$]
• 
  // If there is something connected,
  // print the port name and the connections. 
  if ((connected_to_list.size() > 0) || (provided_to_list.size() > 0) ) begin 
  // Print the name of the port. $display("%s Port: %s", {depth+2{" "}},
  children[i].get_full_name()); end 
  
• how to trace transactions
• use backdoor to log the analysis point
• fifo.put_export.debug_connected_to(); fifo.put_export.debug_provided_to();
• $display("%s", tx_queue[tx_id].convert2string());
• atomic transaction items(active sequence)
• use "pre_body()" phase to add new sequence
• use "post_body()" phase to remove sequence
• active_sequenves::show();
• internal BB(break) point(assertion pp)
• `define BB if (BB::check_pp1( tx, get_full_name()) $stop;
• use "grep" command to filter out the useful info
• grep "type_id::create" xx.log
• use report catcher without default UVM_report, collect the report pool meg to our report format
• function action_e catch();
• id = get_id(); 
• filename = get_fname(); 
• line = get_line(); 
• severity = get_severity();
• $dispay("%s...,", id);
• use report server to overwrite the report

ref: Better Living Through Better Class-BasedSystemVerilog Debug

example MyHDL

hi all,

this is a speech about MyHDL in python taipei meeting,
the free project code can download from git
thanks

python + google GAE + checkIO

底下用就用 checkIO ATM + Google GAE(guestbook) 來當今天的玩具好了. 主要改寫 checkIO ATM 的 input/output parts 跟 GAE 的 db handle 部分. 除了可以練習一下 GAE,也可以玩 checkIO 裡的習題.

input   : Web text form
output : results

def checkio_atm(data):
    try:
        data = str(data).replace(' ','').replace('[','').replace(']','')
 datas = [int(d) for d in data.split(",")]
 balance, withdrawal = datas[0], datas[1:-1]
 for a in (0.5 + 1.01*it for it in withdrawal if it %5 ==0):
    balance = floor(balance - a) if balance > a else balance
    return "input = %s, rst = %s" %(data,str(balance))
    except:
     return "CheckIO ATM Error"

GAE key notes

• python
• python 2.5 python2.7
• data store
• GQL 
• protocol
• WSGI
• env config set
• yaml 
• How to use ?
• tutorial 1
• tutorial 2
• tutorial 3
• sample code

Html key notes

• css 
• html embedded query  

project download

register allocation and reduction lecture

0015.register allocation-graph-coloring

View more presentations from sean chen.

Scheduling and Allocation lecture

0006.scheduling not-ilp-not-force

View more presentations from sean chen.

Static Single Assignment Form lecture 07 class

definition
SSA
dominator frontier
dominator
Phi node insert

Lecture07

View more documents from sean chen.

Ref: http://www.cis.upenn.edu/~cis570/schedule.html

Introduction to Data-flow Analysis lecture 04 class

definition
def
use
liveness
gen
kill

Lecture04

View more documents from sean chen.

Ref: http://www.cis.upenn.edu/~cis570/schedule.html

Control-Flow Analysis lecture 03 @ class

definition
CFG
loop natural
dominator

Lecture03

View more documents from sean chen.

Ref: http://www.cis.upenn.edu/~cis570/schedule.html

Loop unswitching

# Original
# int i, w, x[1000], y[1000];
#  for (i = 0; i < 1000; i++) {
#    x[i] = x[i] + y[i];
#    if (w)
#      y[i] = 0;
#  }
#
#----------------------------------
# Loop unswitching
#
#  int i, w, x[1000], y[1000];
#  if (w) {
#    for (i = 0; i < 1000; i++) {
#      x[i] = x[i] + y[i];
#      y[i] = 0;
#    }
#  } else {
#    for (i = 0; i < 1000; i++) {
#      x[i] = x[i] + y[i];
#    }
#  }

1.可確保在for loop 中的 lp_body 是 clean 的,
  表示在 lp_body 中,只有 DFG 的 (BasicBlock)BB, 可避免不必要的條件中斷(Branch).

2.可透過 struct 的分析,把 for loop 當成個 node, 可以簡化成 sample BB with CFG control.
之後利用 BDD (Binary decision diagram) 的方式做出每個 Output condition 的機率,
有利於 compiler 做 branch jump 的 predict

x1,x2,x3,Y
---------
[0,0,0] = 0
[0,0,1] = 0 
[0,1,0] = 1
[0,1,1] = 1
[1,0,0] = 1
[1,0,1] = 1
[1,1,0] = 1
[1,1,1] = 0

@ y = 0 prb(3/8)
@ y = 1 prb(5/8) <= predict better

3. key notes
判斷 condition branch 是否 stable, 會不會在 for loop 內改變狀態, 如果是 stable 才做 Loop unswitching