xilinx AXI interconnect

key notes

• cascade AXI bus if the input port > 4 (crossbar) multi to one
• traffic gen for DDR protocol (align burst length to 8), from AXI 2 DDR 
• example:
• 16 streams of 1920x1080 60/75p video information with up to 32 bits/pixel can be handled by a single 64-bit DDR3 interface
• VDMA
• Test Pattern Generators (TPGs) 
• Video Timing Control (VTC) 
•  On-Screen Display (OSD) 
• performance
• 622MB/s 
• 16 streams through memory, or nearly 9.95 GB/s (80 Gb/s)! This 18-port shared memory controller is used to support the 16 VDMA channels
• a memory clock speed of 800 MHz (1,600 MHz data rate).The primary internal AXI4 slave interface of the memory controller is operated at 200 MHz, using an AXI4 data width of 512 bits, supporting a theoretical maximum data bandwidth of 12.8 GB/s

refs: http://www.xilinx.com/support/documentation/white_papers/wp417-Xilinx-AXI4-Interconnects.pdfhttp://www.xilinx.com/support/documentation/application_notes/xapp521_XSVI_AXI4.pdf
http://www.xilinx.com/support/documentation/ip_documentation/ug761_axi_reference_guide.pdf