AXI BFM(bus function model)

• standard protocol
• write phase (fork events)
• write address phase
• collect transactions when AXI_AWVALID and AXI_AWREADY
• write data phase
• collect transactions when AXI_WVALID and AXI_WREADY
• write response phase
• collect transactions when AXI_BVALID and AXI_BREADY
• the valid transaction should have the same ID at address, data, response 
• 
  
• read phase(fork events)
• read address phase
• collect transactions when AXI_ARVALID and AXI_ARREADY
• read data phase
• collect transactions when AXI_RVALID and AXI_RREADY
• the valid transaction should have the same ID at address, data
• extend protocol
• qos
• user
• region
• lock
• cache
• strb
• https://github.com/funningboy/axi-bfm

UVM notes

UVM

• virtual interface
• interface define
• modports(define the port type for master/slave)
• master (input,output), slave(input, output)...
• task trigger
• task req;
  `uvm_info(get_full_name(),"start req",UVM_LOW);
  vif.req <= 1b'1;
  @(posedge vif.clk);
  while(!vif.ack) @(posedge vif.clk)
  vif.req <= 1'b0;
  `uvm_info(get_full_name(),"end req",UVM_LOW);
  end_task
• protocol assertion
• assert
• timing constrain
• setup time, hold time, sample rate, clock rate
• http://learn-systemverilog.blogspot.tw/2010/07/writing-systemverilog-assertion-for.html
• UVM_Transfer
• transfer type, contain definition
• common
• transaction id, transaction type, begin time, end time
• base extends common
• such as : address, RW type, Data byte array, burst size
• UVM_Agent
• support monitor, (driver, sequencer) if the active option is on
• UVM_monitor
• collect pin level info to transaction level info
• export transaction analysis port to TLM2.0 SystemC or scoreboard 
• protocol coverage like burst len need to support 1,2,4,8,16....
• UVM_driver
• driver the test sequence lib to virtual interface
• UVM_sequencer
• task item manager 
• sort the sequences by it's own priority or set it's dependence condition or it's spawn event
• UVM_scoreboard
• check transaction is completed from master to slave or slave to master
• UVM_test
• define testsuites like "read_after_write", "normal test", "critical test"...
• UVM_env
• test env build up.
• modules
• config
• module
• config address range, RGM
• transaction
• config type, info, address, data, len...
• system
• whole design config
• UVM_package
• pack lib 

Assertions

• coverage assertion
• coverage group
• FSM group
• pattern group
• functional assertion
• c/c++ co-sim 
• phase to phase check
• DPI wrapper interface
• SystemC TL0/TL1 co-sim
• use TLM2.0 analysis port export 
• protocol assertion
• req/grant
• @(posedge clk) req |-> [1:3]gt;

UVM systemverilog assertion(SVA)

• assertion
• assert in C/C++, pointer check 
• A *a = new A();
• assert(a!=NULL);
• a->do_some_thing()...
• main purpose
• performance hazards
• performance requirement throughput for real time issue
• wrong functionality
• functional error when the transaction is miss-match for each condition description
• Assertion active at both clock edges
• a2: assert property(@(posedge clk)a|->b[*8]); 
• Sequence used as clocking event 
• sequence s;
  @(posedge clk) a[*5];
  endsequence
  a3: assert property (@(s) b |-> ##3 c); 
• Complex Boolean expression used for clock 
• a5: assert property (@(clk iff en) p1);    
• Wrong argument type or size
• `ASSERTS_ONE_HOT(a7, {sig1, sig2, sig3} ...);    
• short circuit 
• function bit legal_state(
• bit [0:3] current, bit valid);
• a12: assert #0 (valid |-> current != '0);
• legal_state = valid && $onehot(current);
• endfunction
• …
• if (status || legal_state(valid, state)) 
  
• Action block without functional call
• `define MY_MUTEX(sig) \
• assert #0($onehot0(sig))
• always @(posedge clk) begin
• ...
• `MY_MUTEX(fsm_1_state)
• `MY_MUTEX(fsm_2_state); 
• end
• req/grant protocol check
• a14: assert property
• (@clk req |-> strong(##[1:$] gnt));
• assertion for coverage
• c16: cover property (@clk 
• (state==REQ)##1 (state==SEND));
•  possibly ignored assertions
• low coverage(pattern valid/invalid, critical case, how to inc the coverage value)
•