SystemVerilog parallel tasks by event trigger

SystemVeilog event trigger is implemented by event manager, that can define the dependences of parent and child tasks. and each tasks will be registered in event list when the building phase is done, after it, the task manager will sort event list by it's dependence or timing (such as E(timing(0)(0)), E(timing(1)(1)) E0 > E1, E0 will be run first than E1.

AXI write phase example. using delay constrain to define which one is first, which one is second

// @ write phase before write addr phase
// cfg.write_addr_delay = 10;
// cdg.write_data_phase = 0;


// @ write phase after write addr phase
// cfg.write_addr_phase = 0;
// cfg.write_data_phase = 10;

task run_phase();
  fork
    write_addr_phase();
    write_data_phase();
    get_next_trx();
  join
endtask


task get_next_trx();
  forever begin
    @(posedge vif.clk);
    if (sequencer.item.has_next_trx()) begin
      trx = sequencer.item.get_next_trx();
      if (trx.rw == `WRITE)
        -> start_write;
      else
        -> start_read;
    end 
  end 
endtask

task write_addr_phase();
  forever begin
    if (start_write.triggered) begin
      repeat(cfg.write_addr_delay) @(posedge vif.clk);
      // do write phase
    end 
  end 
endtask

task write_data_phase();
  forever begin
    if (start_write.triggered) begin
      repeat(cfg.write_data_delay) @(posedge vif.clk);
      // do data phase
  end 
endtask

PyHVL = verilog PLI is going died....

• open source tool supported 
• iverilog VPI 2.0 
• http://iverilog.wikia.com/wiki/Using_VPI
• what's VPI/PLI(Verilog Procedural Interface)
• http://en.wikipedia.org/wiki/Verilog_Procedural_Interface
• what's DPI(SystemVerilog Direct Programming Interface)
• http://en.wikipedia.org/wiki/SystemVerilog_DPI
• third party language support 
• perl
• http://www.veripool.org/wiki/verilog-pli/Manual-verilog-pli
• ruby
• http://snk.tuxfamily.org/lib/ruby-vpi/
• python
• http://sourceforge.net/projects/pyhvl/?source=dlp
• disadvantage
• hard to read
• more rules need to follow
• init pli
• register pli 
• free pli
• using third part language to mix simulation run that's very difficult for designer view. they need to know how to driver system call and catch the simulation error when the segment fault happened 
• c 
• only for behavior model verification / profile
• why not using SystemVerilog + DPI to replace it?
• more closer with Verilog language
• more easily to understand 
• OO suport
• more flexible to designer(customer DPI)
• UVM 

AXI BFM(bus function model)

• standard protocol
• write phase (fork events)
• write address phase
• collect transactions when AXI_AWVALID and AXI_AWREADY
• write data phase
• collect transactions when AXI_WVALID and AXI_WREADY
• write response phase
• collect transactions when AXI_BVALID and AXI_BREADY
• the valid transaction should have the same ID at address, data, response 
• 
  
• read phase(fork events)
• read address phase
• collect transactions when AXI_ARVALID and AXI_ARREADY
• read data phase
• collect transactions when AXI_RVALID and AXI_RREADY
• the valid transaction should have the same ID at address, data
• extend protocol
• qos
• user
• region
• lock
• cache
• strb
• https://github.com/funningboy/axi-bfm