python unittest + UVM testsuites + Jenkins = DUT regression

in recently, i got a order from my boss. he asked me to build up a automatically unittest env that can very quick to know where is the problem such as protocol error, functional error, timing error ... when the design is changed. the below list is my auto regression flow and requirements

• i used python unittest to our based unittest framework
• python unittest
• check testsuite is pass/fail
• python nose 
• call python unittest folder and testsuites
• python subprocess/multiprocess
• call system call (irun, vcs....)
• python re(regular expression)
• check simulation result is pass/faill if the error tokens are not found
• 
  
• UVM testsuites
• define UVM test sequence for your simulator
• irun -uvm +UVM_TESTNAME=""...
• prepare your test sequence
• like xxSequences.sv
• test_1read_after_1write
• test_mread_after_mwrite
• test_read_write_at_same_time
• jenkins
• job manager
• daily regression run 

Microsemi BFM script language

• a very useful script language for bus performance estimation and bus functional check
• example:

• # read B uart 0;
  Reading offset 0 of uart – data = 0x1c
  # write B uart 4 bb;
  Writing 0xbb to offset 4 of uart
  # read B uart 8;
  Reading offset 8 of uart – data = 0x28
  # write B mac 30 11;
  Writing 0x11 to offset 30 of mac
  # readcheck B mac 11;
  Reading offset 0 of mac
  Error: Expected data = 0x11, Actual data = 0x22
  Test Failed, with 1 error

• 
  

• advantage
• simple 
• error check 
• disadvantage
• no time stamp
• maybe it use ASAP(as soon as possible) methodology to transfer transactions, it means masters or slaves are not in busy status, or fetch/push buffers not full
• no atomic transfer
• if valid/ready is not continuous in the burst transaction, the interlevel transactions will happened, 
• like A1(4), A2(4), A1 has burst 4 trxs, A2 has burst 4 trxs.
• A1(2), A2(2), A1(2), A2(2) => atomic transactions when the A1 or A2 has busy or error in the internal transaction.
• 
  

synplify + ise TCL xflow

http://outputlogic.com/xcell_using_xilinx_tools/74_xperts_04.pdf https://github.com/dlitz/openmsp430/blob/master/core/synthesis/actel/synplify.tcl https://github.com/martinjthompson/VHDL-compare/blob/master/Synplify/rev_1/run_ise.tcl https://github.com/martinjthompson/VHDL-compare/tree/master/Synplify https://github.com/zakiali/pocket_corr/blob/master/pfb_core/SgIseProject.tcl