UVM TLM2.0 notes

if your are a ESL designer, you may heard about the SystemC TLM2.0 model that can help designer to design system level evaluation models very quick without any detail info such as Pin assignment, protocol selected, timing(real).... as you known, if you can use these abstract level api(blocking_trans, non_blocking_trans), you can replay or remodel design very quick without reconstruct your design again when the project is in evaluation phase. right now you can migrate your design from SystemC to UVM1.1d, because UVM1.1d is based on SystemVerilog that can be more suitable for EDA vendor supported and more friendly for verification designer... that's my guess ...


socket channel connection
initiator_socket : as same as master socket
target_socket    : as same as slave socket

ex:
1. create sockets in master/slave sides
initiator_socket ini_socket; // master socket
target_socket tgt_socket; // slave socket

connect(ini_socket, [tat_socket,...]) // connect one master to multi slaves

2. create trx payload to socket channel in master side
Trx trx = new();
trx.addr = 0x100;
trx.data = [0x1, 0x2, 0x3]; // generation payload
init_socket.write(trx);

3. collected trx in slave side
trx = tgt_socket.get_trx();     // fetch trx from socket channel fifo, and double check the trx is valid
if (trx != NULL) { // do something .... }


4. blocking trx
blocking interface conveys transactions in blocking fashion; its methods do not return until the transaction has been successfully sent or retrieved.  Because delivery may consume time to complete, the methods in such an interface are declared as tasks

5. non blocking trx
A non-blocking interface attempts to convey a transaction without consuming simulation time.  Its methods are declared as functions.  Because delivery may fail (e.g. the target component is busy and can not accept the request), the methods may return with failed status.

6. port, export, imps
port: instantiated in components that require, or use, the associate interface to initiate transaction requests. export : instantiated by components that forward an implementation of the methods defined in the associated interface. The implementation is typically provided by an imp port in a child component.

deep copy or shadow copy in your systemverilog object

as the same methodology as c/c++ or any languages. we usually used copy function to copy trx to avoid the overwrite trx when the trx had new ptr triggered. this is an sample example about what's the difference between deep copy and shadow copy, in short word. deep copy is top down copy, copy from this(current) level info to it's parents info. shadow copy is template current level copy, only for this level info.

class Based #(type T=int unsigned);
  T val;

  function new (T v=0);
    val = v; // assign new val
  endfunction : new

  virtual function void deep_copy(Based b);
    assert(b!=null);
    b.val = val; // b.val = this.val
  endfunction : deep_copy

  virtual function void shadow_copy(Based b);
    assert(b!=null);
    b.val = val; // b.val = this.val
  endfunction : shadow_copy

  virtual function bool eq(Based b);
    return b.val == val;
  endfunction : eq

endclass : Based

class A #(type T=int unsigned) extens Based;
  T val_a

  function new (T v=0);
    super.new();
    val_a = v; // assign val_a
  endfunction : new 

  virtual function void deep_copy(A a); 
    assert(a!=null);
    Based b;
    a.val_a = val_a;
    $cast(b,a);
    super.deep_copy(b);
    // or
    // a.val_a = val_a
    // a.val  = super.val
  endfunction : deep_copy

  // operator overwrite ... eq, lt, lt, ...
  virtual function bool eq(A a0);
    assert(a0!=null);
    Based b0;
    $cast(b0,a0);
    return val_a == a0.val_a & super.eq(b0);
  endfunction : eq


endclass : A


A a0 = new(1);
A a1 = new(2);

a0.val_a = 3;
a0.val = 2;

a0.deep_copy(a1);

// check a0, a1 contains are eq  a0 = a1
assert(a0.eq(a1));  

waveform modeling

as well as your are a ATE engineer, you may very familiar with the ATE test pattern formats that can transfer the waveform info into sample digital codes.
this is  a very example code for req/grant test case.

// timing modeling
task req_grant_00();                                                                                                                                                                 
  m_vif.REQ   <= 0;
  m_vif.GRANT <= 0;
  @(posedge m_vif.CLK);
endtask : req_grant_00

task req_grant_01();
  m_vif.REQ   <= 0;
  m_vif.GRANT <= 1;
  @(posedge m_vif.CLK);
endtask : req_grant_01

task req_grant_10();
  m_vif.REQ   <= 1;
  m_vif.GRANT <= 0;
  @(posedge m_vif.CLK);
endtask : req_grant_10

task req_grant_11();
  m_vif.REQ   <= 1;
  m_vif.GRANT <= 1;
  @(posedge m_vif.CLK);
endtask : req_grant_1

task

task wave_gen();
  list = {`ON_OFF, `ON_ON, `OFF_ON, `OFF_OFF};

  foreach(list[i]) begin
    case(list[i])
      `ON_OFF : req_grant_10();
      `ON_ON  : req_grant_11();
      `OFF_OFF: req_grant_00();
      `OFF_ON : req_grant_01();
    endcase
  end 
endtask