Xilinx ucf constrain notes

ucf constrain

• timing constrain
• input pad to first flip-flop groups
• input offset
• internal flip-flop to flip flop groups
• period
• out flip-flop to output pad groups 
• output offset
• clock
• offset
• duty
• jitter
• rotate
• 90 
• 180
• 270
• multi cycle path
• from one clock dom to another clock dom
• using async fifo to avoid the data missing issue
• data valid
• req fifo.empty/fifo.full
• status
• false path
• not normal paths
• -to
• -from -to
• -through
• -from -through -to 
• data path
• normal paths
• fanout
• set maxfanout
• DCM / DLL/ PLL
• ECO div/mux
• TNM (timing group)
• 
  
• pin assignment constrain
• pad assignment 
• 
  
• slack
• Slack (setup path): =  (requirement - (data path - clock path 
• skew + uncertainty))
• Slack (hold path): = requirement - (clock path skew + uncertainty - data path) 

sytemverilog virtual interface setup time hold time check

we use systemveirlog virtual interface and simulator keys $setup, $hold to check the setup/hold time.

interface my_if #(c_clk_high_time = 5,
                  c_clk_low_time  = 5) (input clk, en);
  specify
    specparam clk_high_time = c_clk_high_time;
    specparam clk_low_time = c_clk_row_time;
    $setup(en, negedge clk, clk_high_time * 4 / 5);
    $hold(negedge clk, en, clk_low_time * 4 / 5);
  endspecify

endinterface;

or

module timing_checks_in_sv (input clk, data, ...); 
  ...
  event ev_data_delayed_toggled;
  
  always @(data)
  begin
    fork
    begin
      # tSetup;
      -> ev_data_delayed_toggled;
    end
    join_none
  end

  property setup_hold_time_checker;
    time curr_time;
    @(posedge clk) (1, curr_time = $time) |->
    @(ev_data_delayed_toggled) (($time - curr_time) > (tSetup + tHold)); // check data arrival time is meet $time - cur_time > (SetUp + Hold)
  endproperty : setup_hold_time_checker

  ASSERT_SETUP_HOLD: assert property setup_hold_time_checker;
endmodule 

ref :
http://learn-systemverilog.blogspot.tw/2010/07/writing-systemverilog-assertion-for.html
http://www.ee.ed.ac.uk/~gerard/Teach/Verilog/me5cds/me95rh.html

UVM TLM2.0 notes

if your are a ESL designer, you may heard about the SystemC TLM2.0 model that can help designer to design system level evaluation models very quick without any detail info such as Pin assignment, protocol selected, timing(real).... as you known, if you can use these abstract level api(blocking_trans, non_blocking_trans), you can replay or remodel design very quick without reconstruct your design again when the project is in evaluation phase. right now you can migrate your design from SystemC to UVM1.1d, because UVM1.1d is based on SystemVerilog that can be more suitable for EDA vendor supported and more friendly for verification designer... that's my guess ...


socket channel connection
initiator_socket : as same as master socket
target_socket    : as same as slave socket

ex:
1. create sockets in master/slave sides
initiator_socket ini_socket; // master socket
target_socket tgt_socket; // slave socket

connect(ini_socket, [tat_socket,...]) // connect one master to multi slaves

2. create trx payload to socket channel in master side
Trx trx = new();
trx.addr = 0x100;
trx.data = [0x1, 0x2, 0x3]; // generation payload
init_socket.write(trx);

3. collected trx in slave side
trx = tgt_socket.get_trx();     // fetch trx from socket channel fifo, and double check the trx is valid
if (trx != NULL) { // do something .... }


4. blocking trx
blocking interface conveys transactions in blocking fashion; its methods do not return until the transaction has been successfully sent or retrieved.  Because delivery may consume time to complete, the methods in such an interface are declared as tasks

5. non blocking trx
A non-blocking interface attempts to convey a transaction without consuming simulation time.  Its methods are declared as functions.  Because delivery may fail (e.g. the target component is busy and can not accept the request), the methods may return with failed status.

6. port, export, imps
port: instantiated in components that require, or use, the associate interface to initiate transaction requests. export : instantiated by components that forward an implementation of the methods defined in the associated interface. The implementation is typically provided by an imp port in a child component.