In Soc Design, the timing source is a big problem, because it would influence the data through put rate and correction. in default Soc design, we would put the clock source in one side corner by it's routing tool definition, but the clock paths should from root to leafs, that could supply the whole chip clock to work, so how to keep the cleaning clock and lower hardware cost is our topic ,In here we used Minimum Spanning Tree Algorithm to solve it question.
In pig 1 is our clock tree case, we extend it to each clock leaf clusters, if we define each cluster had it's own clock domain, like C1(533Mhz), C2 (266Mhz) , and each clock domain had it's own clock leaf nodes, so we can use Minimum Spanning Tree to find out our minimum clock source, that means we can get the shortest clock path from clock root(PLL), so the metal line is getting shorter and violation is reduced.
pic 1
in order to reduce power consumed, we could insert some clock gates in the path of clock tree by Latch gate, because the Latch is level sensitive design, it only change it's data by status changed, so it can filter out the violation in input and hold the data stable in output stage.
In Soc Design, the timing source is a big problem, because it would influence the data through put rate and correction. in default Soc design, we would put the clock source in one side corner by it's routing tool definition, but the clock paths should from root to leafs, that could supply the whole chip clock to work, so how to keep the cleaning clock and lower hardware cost is our topic ,In here we used Minimum Spanning Tree Algorithm to solve it question.
In pig 1 is our clock tree case, we extend it to each clock leaf clusters, if we define each cluster had it's own clock domain, like C1(533Mhz), C2 (266Mhz) , and each clock domain had it's own clock leaf nodes, so we can use Minimum Spanning Tree to find out our minimum clock source, that means we can get the shortest clock path from clock root(PLL), so the metal line is getting shorter and violation is reduced.
pic 1
in order to reduce power consumed, we could insert some clock gates in the path of clock tree by Latch gate, because the Latch is level sensitive design, it only change it's data by status changed, so it can filter out the violation in input and hold the data stable in output stage.
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