UVM AXI BFM 1.0 release

supported list

• AXI3/AXI4 bus protocol
• out of order/ inorder transactions
• each write/read phase is independent
• addr/write/resp is independent
• interlevel
• split
• performance watch dog 
• protocol watch dog
• performance report
• MAX, AVG, MIN bus bandwidth
• through put
• transaction list(disassemble bus info)
•  virtual master
• define each phase delay(req to grant or each valid/ready) or drive trx out time stamp
• virtual slave
• define each phase delay(req to grant or each valid/ready) or drive trx out time stamp
• scoreboard
• check connection
• check the memory read write is pass when the read/write trx in the same address, the read trx must be finished first than write trx to avoid the overwrite the address issue.
• STL 
• user define TRX language
• SystemC analysis port 
• user can use analysis port to link third part debug model by using DPI interface like Verilog to SystemC  or Verilog to C/C++
• 
  
• https://github.com/funningboy/uvm_axi

UVM notes 2

• UVM reference flow
• UVM tutorial
• http://cluelogic.com/tag/vmm/UVM_AGENT
• virtual sequencer
• handle each sub sequencers when the platform contains multi sequences to drive the same DUT. 
• avoid race conditions,  transaction sequence, like multi threads system
•  ex:
•       jb_seq1 = same_flavored_jelly_beans_sequence::type_id::create( .name( "jb_seq1" ), .contxt( get_full_name() ) );
•       jb_seq2 = same_flavored_jelly_beans_sequence::type_id::create( .name( "jb_seq2" ), .contxt( get_full_name() ) );
•       case ( recipe )
•         LEMON_MERINGUE_PIE: begin
•            jb_seq1.flavor          = jelly_bean_transaction::LEMON;
•            jb_seq2.flavor          = jelly_bean_transaction::COCONUT;
•            jb_seq1.num_jelly_beans = 2;
•            jb_seq2.num_jelly_beans = 2;
• configure
• set  register , interface from top to down
• test_lib -> test_env -> test_cfg -> test_agent ... 
• ex:
•    initial begin
•       uvm_config_db#( virtual jelly_bean_if )::set
•          ( .cntxt( null ), .inst_name( "uvm_test_top" ), .field_name( "jb_if1" ), .value( jb_if1 ) );
•       uvm_config_db#( virtual jelly_bean_if )::set
•          ( .cntxt( null ), .inst_name( "uvm_test_top" ), .field_name( "jb_if2" ), .value( jb_if2 ) );
•       run_test();
•    end
• register abstract
• check register r/w limitation(only r/w), fields check, width check, coverage, assertion
• ex:
•       flavor = uvm_reg_field::type_id::create( "flavor" );
•       flavor.configure( .parent                 ( this ),
•                         .size                   ( 3    ),
•                         .lsb_pos                ( 0    ),
•                         .access                 ( "WO" ),
•                         .volatile               ( 0    ),
•                         .reset                  ( 0    ),
•                         .has_reset              ( 1    ),
•                         .is_rand                ( 1    ),
•                         .individually_accessible( 0    ) );
• 
  
• assertion
• 
  
• functional coverage

xilinx AXI interconnect

key notes

• cascade AXI bus if the input port > 4 (crossbar) multi to one
• traffic gen for DDR protocol (align burst length to 8), from AXI 2 DDR 
• example:
• 16 streams of 1920x1080 60/75p video information with up to 32 bits/pixel can be handled by a single 64-bit DDR3 interface
• VDMA
• Test Pattern Generators (TPGs) 
• Video Timing Control (VTC) 
•  On-Screen Display (OSD) 
• performance
• 622MB/s 
• 16 streams through memory, or nearly 9.95 GB/s (80 Gb/s)! This 18-port shared memory controller is used to support the 16 VDMA channels
• a memory clock speed of 800 MHz (1,600 MHz data rate).The primary internal AXI4 slave interface of the memory controller is operated at 200 MHz, using an AXI4 data width of 512 bits, supporting a theoretical maximum data bandwidth of 12.8 GB/s

refs: http://www.xilinx.com/support/documentation/white_papers/wp417-Xilinx-AXI4-Interconnects.pdfhttp://www.xilinx.com/support/documentation/application_notes/xapp521_XSVI_AXI4.pdf
http://www.xilinx.com/support/documentation/ip_documentation/ug761_axi_reference_guide.pdf