hi all,
if your are a CAD Engineer in IC design house, i think you always take a lot of time to do recourse jobs... like reassign wire names, add new cells, check netlist...that's really suck things. why not try this tool that can help you insert ECO cell automatically, and double check the ECO cell inserted is ok when you running this script.
features
1. ECO cell insert
2. ECO cell check
3. Module output Fanin check
4. Module input Fanout check
5. cell, port, net, width check
more to do
1. support Graph alg(
NetworkX)
2. support assign statement
3. support STA, Timing check
4. support simulation???
Example:
Definition about input/output, ECO file...
# our org NetList file
vtest = \
"""
module TOP( in, out );
input [1:0] in;
output [1:0] out;
INVD1 U0( .I( in[0] ), .ZN( out[0] ) );
INVD1 U1( .I( in[1] ), .ZN( out[1] ) );
endmodule
"""
# our cell lib file
ytest = \
"""
AN2D1:
inputs:
A1: 1
A2: 1
outputs:
Z: 1
primitive: A1 and A2
INVD1:
inputs:
I: 1
outputs:
ZN: 1
primitive: not I
"""
# our ECO file description, define where is the Input, Output link coming from, and it's assign value
etest = \
"""
AN2D1:
inputs:
A1: new_in
A2: in[0]
outputs:
Z: new_out
primitive: A1 and A2
"""
# our expect value
exptest = \
"""
module TOP( new_in, new_out, in, out );
output [ 1: 0 ] out;
input [ 1: 0 ] in;
input new_in;
output new_out;
AN2D1 ECO_AN2D1( .A1( new_in ), .A2( in[0]), .Z( new_out ) );
INVD1 U0( .I( in[0] ), .ZN( out[0] ) );
INVD1 U1( .I( in[1] ), .ZN( out[1] ) );
endmodule
"""
How to run
Add new ECO cell in org NetList file.
>>> eco = ECO()
>>> eco.readYAML("test/gates.yml") # read cell libs
>>> eco.readVerilog("test/Iface_test.gv") # read org verilog Netlist file
>>> eco.link("Iface_test") # link top module
>>> eco.checkDesign() # check pre load design is ok
>>> eco.report()
>>> eco.readECO("test/ECO.yml") # read eco file
>>> eco.runECO() # run eco
>>> eco.checkDesign() # recheck design again when the ECO is done
>>> eco.report()
>>> eco.writeVerilog("test/new_Iface_test.gv")
How to run unittest
nosetests
project
