python 大補帖 = Anaconda

最近小弟因為要做些圖形應用的 project, 裡面要用到 opencv 跟 big data 相關的 modules, 去幫我做些圖形運算. 但小弟不才, 軟體灌了很久就是裝不起來, 不是東缺一塊就是西塊, 於是就拿出 python 大補帖, 直接install下去, 完全就是快速阿...

• what's Anaconda

• a tool set for big data analysis which is contains (numpy, scipy, panda, pytable)

package list

• http://docs.continuum.io/anaconda/pkgs.html

set up your python path

• ~/.bashrc
• export PATH=~/anaconda/bin:$PATH, export PYTHONPATH=~anaconda/lib/python2.7:$PYTHONPATH

open source

• http://continuum.io/developer-resources

Demo for interview

最近為了 interview 寫了幾個小 project. 有興趣的就參考看看吧！！

jenkins + python = regression env

Hi all,
this is a python unittest regression flow by jenkins that can help designer daily run testsuites and support the GUI output reports(coverage pass rate)

github:

• https://github.com/funningboy/ijenkins/blob/master/README

ref:

• http://jenkins-ci.org/content/python-love-story-virtualenv-and-hudson

xilinx axi bus traffic gen

• AXI4/AXI-stream
• dependent/independent transaction
• initial ram
• error interrupt/ status
• command
• data
• debug
• address gen
• align
• byte 64bit, 32bit...
• un-align
• offset
• type
• inc, wrap, fixed
• data gen
• mem data width
• initial system set
• NOP instruction for dummy loops
• Test DUT performance
• replay Bus transactions when the debugging mode is opened
• 
  
• ref:
• http://www.xilinx.com/support/documentation/ip_documentation/axi_traffic_gen/v1_0/pg125-axi-traffic-gen.pdf

Xilinx Hierarchical_Design_Methodology

• bottom up
• in any conditions should been re-runed partition again
• VHDL/ngc/ngd source changed
• constrains changed
• partition changed
• fpga package changed
• partition(split to small partitions)
• cost, benefit trade off, such as timing area ...
• black box(often used in Memory or fixed devices)
• ngc, ngd
• synthesis token 
• black box syntax in your VHDL like transfer_on, transfer_off
• minimal logic
• small cells. DSP/RAM normal cells
• advantage
• incremental place routing to reduce synthesis time
• no rerun again when it's non-touchable design  
• disadvantage
• the constrains need to be reseted in whole chip view, because in each sub constrains only has it's constrains setting, if some paths from source pad to internal block and this path can cross through two different constrain blocks, it means the sub constrains it seems does't work for this set.
• partition file
• PXML
• synplify smxl2pxml or xilinx xst
• pblock
• reversed place & route block 
• ngc 
• partition cell lib
• BoundaryOpt
• two partition interfaces bridge
• top down

ref:

• http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_3/Hierarchical_Design_Methodology_Guide.pdf
• http://www.xilinx.com/support/documentation/white_papers/wp386_Hierarchical_Design_Synopsys_Xilinx.pdf