Xilinx Hierarchical_Design_Methodology

• bottom up
• in any conditions should been re-runed partition again
• VHDL/ngc/ngd source changed
• constrains changed
• partition changed
• fpga package changed
• partition(split to small partitions)
• cost, benefit trade off, such as timing area ...
• black box(often used in Memory or fixed devices)
• ngc, ngd
• synthesis token 
• black box syntax in your VHDL like transfer_on, transfer_off
• minimal logic
• small cells. DSP/RAM normal cells
• advantage
• incremental place routing to reduce synthesis time
• no rerun again when it's non-touchable design  
• disadvantage
• the constrains need to be reseted in whole chip view, because in each sub constrains only has it's constrains setting, if some paths from source pad to internal block and this path can cross through two different constrain blocks, it means the sub constrains it seems does't work for this set.
• partition file
• PXML
• synplify smxl2pxml or xilinx xst
• pblock
• reversed place & route block 
• ngc 
• partition cell lib
• BoundaryOpt
• two partition interfaces bridge
• top down

ref:

• http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_3/Hierarchical_Design_Methodology_Guide.pdf
• http://www.xilinx.com/support/documentation/white_papers/wp386_Hierarchical_Design_Synopsys_Xilinx.pdf