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2013年6月19日 星期三

high level synthesis with Xilinx

key notes:

  • write your struct ASIC c code, no class...., only for struct supported
    • familiar hardware c (no hierarchal ptr, dynamic/static cast/ptr)
  • implemented module select(architecture set)
    • sub standard cell assign
      •  like a+b  for operator "add", it can be "32bitAdd", or "64bitAdd" ...
    • memory assign
      • internal buffer, (asyn_fifo) for different clock interface
    • for loop extend(unroll)
      • like for (i=0; i < 2; i++), it will be extend to l0, l1, sequences for reschedule, if the data doesn't have any dependence in this loop, that can merge these two sequences in one parallel sequence. 
    • resource constrain
      • area constrain
      • sub cell constrain
      • timing constrain
    • scheduling and binding
      • pipeline
  • implemented protocol interface
    • AXI3/4 AXI stream
    • transfer task assign
      • req/grant
      • burst ... ex: axi_bus_write(addr, [data,..]) => for axi burst write transfer 

  • RTL code gen
    • verilog/systemc
  • report
    • trade off
      • performance/area
    • simulation time estimation
      • delay 
    • area estimation
      • size
  • refs:
    • http://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_2/ug902-vivado-high-level-synthesis.pdf
    • http://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_2/ug871-vivado-high-level-synthesis-tutorial.pdf
    • http://www.xilinx.com/support/answers/50929.html

2013年5月17日 星期五

UVM scoreboard to check with c/c++ golden model via uvm analysis port

1.systemverilog DPI interface to interconnect the c/c++ part and systemverilog part

2.uvm analysis port to valid event channel
// golden cehck via uvm analysis port
// ps : the port should be connected to it's callback module. that uvm can collected.
// ex: item_port.connect( analysis_export );

uvm_analysis_port item_port

// DPI import ... for our golen model
import "DPI" void *yuv2rgb(int unsigned y, int unsigned u, int unsigned v);  
// yub2rgb(void* trx); using ptr is a more friendly interface....
import "DPI" void *rgb2yuv(int unsigned r, int unsigned g, int unsigned b); 

// callback func called from callable func/module
task callback(sample_trx trx);

  assert(trx!=null);
  if (trx.type == YUV2RGB)
    dpi_c_yuv2rgb(trx);
  else
    dpi_c_rgb2yuv(trx);

endtask

void dpi_c_yuv2rgb(sample_trx trx);
                                                                                                                                                                                    
  assert(trx!=null);
  c_rst = yuv2rgb(trx.y, trx.u, trx.v)
  assert( c_rst.r == trx.r &
          c_rst.g == trx.g &
          c_rst.b == trx.b);
endtask

2013年5月16日 星期四

adding performance monitor to your design

the UVM monitor can play not only a functional checker but also a performance checker which means, user can use it more quickly to find out where is their design bottleneck without waveform tracing. in this topic, we focused on how to use UVM monitor to point out the collected transactions had timing violation immediately when the simulation was running.

we write a UVM SystemVerilog "req happened until grant received" to our demo case.

 
// spawn sub procs(threads)                                                                                                       
task run_phase(uvm_phase);
  fork
    sent_req();
    sent_grant();

    collected_req();
    collected_grant();

    check_performance();
    check_protocol();
  join
endtask : run_phase


// sent req 
task sent_req();

  forever begin
    // random  wait ....
    repeat($urandom_range(8,16)) @(posedge m_vif.CLK);

    // sent req 
    `delay(conf.half_cycle);
    m_vif.REQ <= `TRUE;
    @(posedge m_vif.CLK);

    // wait until grant received
    while(!m_vif.GRANT) @(posedge m_vif.CLK);

    // free req 
    `delay(conf.half_cycle);
    m_vif.REQ <= `FALSE;
    @(posedge m_vif.CLK);

  end

endtask : sent_req


// snet grant
task sent grant();

  forever begin

    // sent unvalid grant
    `delay(conf.half_cycle);
    m_vif.GRANT <= `FALSE;
    @(posedge m_vif.CLK);

    // wait until req received
    while(!m_vif.REQ) @(posedge m_vif.CLK);

    // random wait ...
    repeat($urandom_range(8,16)) @(posedge m_vif.CLK);

    // sent valid grant to free req
    `delay(conf.half_cycle);
    m_vif.GRANT <= `TRUE;
    @(posedge m_vif.CLK);

  end

endtask : sent grant                                                                                                              


task collected_req();

  forever begin
     // @ neg edge check
      @(negedge m_vif.CLK iff m_vif.REQ);

      // assert only one fifo deep when req/grant case
      assert(m_trx_q.size() < 1);

      // collect trx
      TRX m_trx = new();
      m_trx.REQ = m_vif.REQ;
      m_trx.TIME = $time;
      m_trx_q.push_back(m_trx);

  end
endtask : collected_req


task collected_grant();

  forever begin
    // @ neg edge cehck
    @(negedge m_vif.CLK iff m_vif.GRANT);

    //assert the queue size must be 1, means the req has been stored in the queue
    assert(m_trx.q.size() == 1);

    // free queue
    m_trx_q.pop_front();

  end
                                                                                                                                  
endtask : collected_grant


task check_performance();
  forever begin
    // at each pos edge check
    @(posedge m_vif.CLK);

    //assert queue
    if (m_trx_q.size() == 1) begin
        if ($time - m_trx_q[0].TIME > conf.min_offset) begin
          `uvm_error(get_full_name(), {$psprintf("out of time %d"), conf.min_offset}, UVM_LOW)
        end else begin
          `uvm_error(get_full_name(), {$psprintf("req/grant seuence is not valid")}, UVM_LOW)
        end
    end
  end

endtask             

2013年5月1日 星期三

PyHVL = verilog PLI is going died....


  • open source tool supported 
    • iverilog VPI 2.0 
      • http://iverilog.wikia.com/wiki/Using_VPI
  • what's VPI/PLI(Verilog Procedural Interface)
    • http://en.wikipedia.org/wiki/Verilog_Procedural_Interface
  • what's DPI(SystemVerilog Direct Programming Interface)
    • http://en.wikipedia.org/wiki/SystemVerilog_DPI
  • third party language support 
    • perl
      • http://www.veripool.org/wiki/verilog-pli/Manual-verilog-pli
    • ruby
      • http://snk.tuxfamily.org/lib/ruby-vpi/
    • python
      • http://sourceforge.net/projects/pyhvl/?source=dlp
  • disadvantage
    • hard to read
      • more rules need to follow
        • init pli
        • register pli 
        • free pli
      • using third part language to mix simulation run that's very difficult for designer view. they need to know how to driver system call and catch the simulation error when the segment fault happened 
      • only for behavior model verification / profile
      • why not using SystemVerilog + DPI to replace it?
        • more closer with Verilog language
        • more easily to understand 
        • OO suport
        • more flexible to designer(customer DPI)
        • UVM 

2013年3月28日 星期四

UVM notes 1


  • Ref:
  • transaction and sequence
    • transactions level info
      • collect pin level info to transaction package info, like AXI, req, data, reps, phase for one valid transaction

    • sequence
      • a lots of transactions
        • read/write with burst/2D ...
    • ex:
      • jb_tx = jelly_bean_transaction::type_id::create(.name('jb_tx'), ...); 
      • #create transaction
      • start_item(jb_tx);
      • #start transaction and send it to sequence_item
      • finish_item(jb_tx);
      • # end of transaction
  • agent
    • verification module that contains
      • monitor module(collect transaction)
      • sequencer module(sequence_item handler)
      • driver module(drive transaction to virtual interface)
    • ex: 
      • jb_ap = new(.name('jb_ap'). parent(this));
      • jb_seqr = jb_sequencer::type_id::create(.name('jb_seqr'), .parent(this));
      • jb_drvr = jb_driver::type_id::create(.name('jb_drvr'), .parent(this));
      • jb_mon = jb_monitor::type_id::create(.name('jb_mon'),.parent(this));
      • #build up each sub modules  @build_phase

      • jb_drvr.set_item_port.connect(jb_seqr.seq_item.export);
      • jb_mon.jp_ap.connect(jb_ap);
      • #connect ports and interface @connect_phase

      • #check conf(RGM) and interface is ok @build__phase or end_of_elaboration_phase
  • environment
    • build up test env 
      • Agents
      • Scoreboard
        • record/check each transaction from master to slave is correct, if the transaction is error or out of time. show up some UVM_ERROR message to log file. 
      • ex:
        •   if (  !find_tx_in_jb_queue(tx) ) `uvm_error("trs not found..")
  • package  
    • build up 'import package' for each protocol or special purpose.
      • `include "axi_driver.sv"
      • ....
      • `include "axi_env.sv"
    • ex:
      • import AXIPacakge::* #AXI standard protocol 
  • test_lib
    • build up test env 
      • configure set
        • address range
        • register fields
      • ex:
      • uvm_config_db#(jelly_bean_configuration)::set
      •            (.cntxt(this), .inst_name("*"), .field_name("config"), .value(jb_cfg));
  • analysis_port(binding analysis port to analysis_export)
    • easily to analysis and trace
      • systemverilog tlm package socket to systemc socket
    • analysis_port, analysis_export
    • ex:
      • jb_ap.write(jb_tx);
      • # write transaction to analysis port
      • jb_ap.connect(jb_sub.analysis_export)
      • # connect analysis port to export in connect phase


2013年2月12日 星期二

python + SystemC = pySystemC

Wrapper SystemC TLM models in Python

  • How to install SystemC TLM models in MAC
    • download SystemC2.3
    • cd $
    • %mkdir build
    • %cd  build
    • %../configure
    • %make install
    • %export SYSTEMC_HOME=$
    • cd $/examples/tlm/build-unix
    • replace Makefile.config TARGET_ARCH ?= macosx64
    • make install

  • embedded SystemC to python env

    • advantages
      • script language easy to extend
      • more libraries support
      • more easily to reuse and rebuild(no compiler knowledge)
    • swig
  • how to do it?
    • wrapper SystemC thread/method to python call back
      • void sc_module_swig::method (PyObject * f){
        sc_python_callback * callback =
        new sc_python_callback (f);
        PyObject* name = PyObject_GetAttrString (f,"__name__");
        if(name == NULL || !PyString_Check(name)){
        std::cerr << "python name error\n";
        return;
        }
        sc_method_handle handle = simcontext()->
        register_method_process(
        PyString_AsString (name), callback,this );
        sc_module::sensitive << handle;
        sc_module::sensitive_pos << handle;
        sc_module::sensitive_neg << handle;
        }

    • wrapper SystemC start/end simulation

      • class sc_module_swig : public sc_module {
        public:sc_module_swig (const char * nm): sc_module ((sc_module_name)nm){}

        virtual void beforeEndOfElaboration(){}
        virtual void endOfElaboration(){}
        virtual void startOfSimulation(){}
        virtual void endOfSimulation (){}

        inline void dontInitialize ()
        {sc_module::dont_initialize ();}

        inline sc_sensitive & getSensitive (){return sensitive;}
        ...
        protected:
        inline void before_end_of_elaboration()
        {this->beforeEndOfElaboration ();}
        inline void end_of_elaboration()
        {this->endOfElaboration ();}
        inline void start_of_simulation()
        {this->startOfSimulation ();}
        inline void end_of_simulation()
        {this->endOfSimulation ();}
        ...
        };
    • wrapper SystemC module
      •                                                                                                                                                                  
    • set up SystemC map table "*.i"
      • %module sc_module_swig
        %{
        #include "systemc.h"
        #include "sc_module_swig.h"
        %}

        %include "sc_module_swig.h"
    • swig -c++ -I" -python *.i
  • ref

GreenScript User Manual - GreenSocs

2013年2月10日 星期日

SystemC TLM2.0 notes

TLM2.0 key notes

  • byte enable
  • endianness
  • generated payload (TRS)
  • extension generated payload(transaction ID)
  • socket base transaction
  • transaction traceback (watch monitor)
  • score board recorder 
  • assertion 
  • coverage  
  • b_transaction(blocking)[LT]
    • no direction
    • wait
    • no method sensitive 
    • no pipe
    • no phase
    • no life time
  • nb_transaction(noblocking)[APT](phase),
    • nb_transaction_fw(forward) / nb_transaction_bw(backward)
    • no wait
    • method/thread sensitive
    • pipe
    • phase (req_bg/ed, data_bg/ed, resp_bg/ed) 
    • life time
  • modify 
    • target    (response pp, extension pp)
    • initiator (address, command, data, pp)
    • interconnect (address, extension pp)
  • notify
    • .notify() to switch event and reschedule event lists 
  • free/release pp(pp memory manager)
    • free pp by life time 
  • DMA(direct mem access)
  • data pointer / shared pp deep shadow copy
  • interface (analysis_interface, debug_interface)
  • socket 

LT(loosely time), APT(approximate time), CAT(cycle accurate time)
Tl3(packetize), Tl2(transaction level), Tl1(adaptor Tl1toTl2, Tl2toTl1), Tl0(pin level assign)
TRS (transaction)
carbon design AXI TLM2.0
greensoc OCP TLM2.0