UVM notes 1

• Ref:
• UVM reference flow
• UVM tutorial
• http://cluelogic.com/tag/vmm/UVM_AGENT
• 
  
• transaction and sequence
• transactions level info
• collect pin level info to transaction package info, like AXI, req, data, reps, phase for one valid transaction


• sequence
• a lots of transactions
• read/write with burst/2D ...
• ex:
• jb_tx = jelly_bean_transaction::type_id::create(.name('jb_tx'), ...); 
• #create transaction
• start_item(jb_tx);
• #start transaction and send it to sequence_item
• finish_item(jb_tx);
• # end of transaction
• agent
• verification module that contains
• monitor module(collect transaction)
• sequencer module(sequence_item handler)
• driver module(drive transaction to virtual interface)
• ex: 
• jb_ap = new(.name('jb_ap'). parent(this));
• jb_seqr = jb_sequencer::type_id::create(.name('jb_seqr'), .parent(this));
• jb_drvr = jb_driver::type_id::create(.name('jb_drvr'), .parent(this));
• jb_mon = jb_monitor::type_id::create(.name('jb_mon'),.parent(this));
• #build up each sub modules  @build_phase
• 
  
• jb_drvr.set_item_port.connect(jb_seqr.seq_item.export);
• jb_mon.jp_ap.connect(jb_ap);
• #connect ports and interface @connect_phase
• 
  
• #check conf(RGM) and interface is ok @build__phase or end_of_elaboration_phase
• environment
• build up test env 
• Agents
• Scoreboard
• record/check each transaction from master to slave is correct, if the transaction is error or out of time. show up some UVM_ERROR message to log file. 
• ex:
•   if (  !find_tx_in_jb_queue(tx) ) `uvm_error("trs not found..")
• package  
• build up 'import package' for each protocol or special purpose.
• `include "axi_driver.sv"
• ....
• `include "axi_env.sv"
• ex:
• import AXIPacakge::* #AXI standard protocol 
• test_lib
• build up test env 
• configure set
• address range
• register fields
• ex:
• uvm_config_db#(jelly_bean_configuration)::set
•            (.cntxt(this), .inst_name("*"), .field_name("config"), .value(jb_cfg));
• analysis_port(binding analysis port to analysis_export)
• easily to analysis and trace
• systemverilog tlm package socket to systemc socket
• analysis_port, analysis_export
• ex:
• jb_ap.write(jb_tx);
• # write transaction to analysis port
• jb_ap.connect(jb_sub.analysis_export)
• # connect analysis port to export in connect phase


•