xilinx axi bus traffic gen

• AXI4/AXI-stream
• dependent/independent transaction
• initial ram
• error interrupt/ status
• command
• data
• debug
• address gen
• align
• byte 64bit, 32bit...
• un-align
• offset
• type
• inc, wrap, fixed
• data gen
• mem data width
• initial system set
• NOP instruction for dummy loops
• Test DUT performance
• replay Bus transactions when the debugging mode is opened
• 
  
• ref:
• http://www.xilinx.com/support/documentation/ip_documentation/axi_traffic_gen/v1_0/pg125-axi-traffic-gen.pdf