Force-Directed Scheduling with golden check @ perl

在之前的 post Force-Directed Scheduling with high level synthesis @ perl 中已經完成了 Force-Directed scheduling 核心部份.而這邊主要是 architecture gen 跟 SystemC map. 主要概念如下圖. architecture (CTL) 會根據每個 cycle step 來決定哪個 processor element 要 work. 等全部運算完後會把 DON 拉成 true 給 test bench. 且在下個 cycle 把算完的 data 讀入. 最後再跟 golden model 比對,做 function check.

# @ author: funningboy
# @ email : funningboy@gmail.com
#     syntax2SystemC  flow

use Data::Dumper;
use SysPerl::syntax2DFG;
use SysPerl::constrain2DFG;
use SysPerl::schedule2DFG;
use SysPerl::arch2DFG;
use strict;

#===================================
# @step 1 : gen simple DFG graph
# return  : DFG graph
#         : vertex_pre_stack
#         : vertex_nxt_stack
#===================================
#
#  c = (a+b)>>1;
#  d = w*(a-b);
#  e = d-c-g*c;

my $tt = ['c','=','(','a','+','b',')','>>','1',';'];
my $cc = ['d','=','w','*','(','a','-','b',')',';'];
my $gg = ['e','=','d','-','c','-','g','*','c',';'];
#my $gg = ['e', '=', 'e', '+', '1', ';'];

my $syn  = SysPerl::syntax2DFG->new();
  $syn->read_text($tt);
  $syn->run_text();
  $syn->free();

  $syn->read_text($cc);
  $syn->run_text();
  $syn->free();

  $syn->read_text($gg);
  $syn->run_text();
  $syn->free();

#   my $graph = $syn->get_deep_copy_graph(); 

# remove tmp_reg && feedback assign
# ex : d=c;
#      e=d+1;
   $syn->run_updt_DFG();

# get all graph && DFG flow 2 schedule
my $DFG = $syn->get_deep_copy_DFG();

# dump graph as dot file   
 $syn->dump_DFG_graphviz_file('syn2DFG.dot');
 $syn->free();

#=====================================
# @step2. :
# flow 1  : insert time weighted constrain 2 simple DFG graph and
#           gen Cstep graph(cycle step grpah)
# flow 2  : insert average power weighted constrain 2 Cstep and gen the force vale
#           @ force directed scheduling
# return :  cycle graph
#=====================================
# set unit time wait delay
my $constrain_time_weighted_vertices = {
    '+'  => 1,   # add delay 1 unit s
    '-'  => 1,   # sub delay 1 unit s
    '*'  => 2,   # mul
    '/'  => 2,   # div
    '%'  => 2,   # rem
    '>>' => 1,   # rsht
    '<<' => 1,   # lsht
};

#set unit average power consumed
my $constrain_power_weighted_vertices = {
    '+'  => 4,
    '-'  => 4,
    '*'  => 8,
    '/'  => 10,
    '%'  => 10,
    '>>' => 1,
    '<<' => 1,
};

my $con = SysPerl::constrain2DFG->new();
  $con->set_deep_DFG($DFG);

  $con->set_constrain_time_weighted($constrain_time_weighted_vertices);
  $con->set_constrain_power_weighted($constrain_power_weighted_vertices);

  $con->run_constrain_time_weighted_DFG();
  $con->run_constrain_NewDFG();

#   $con->dump_ALUDFG_graphviz_file('alu.dot');
  $con->dump_NewDFG_graphviz_file('con.dot');

#=============================
# schedule && cluster
#=============================
my $sch = SysPerl::schedule2DFG->new();
  $sch->set_deep_cons2DFG($con);

  $sch->run_forece_directed_scheduling();
  $sch->report();

#=============================
# explore hardware
#============================= 
my $arc = SysPerl::arch2DFG->new();
  $arc->set_deep_sched2arch($sch);
  $arc->run_ALU_cluster();
  $arc->run_explore_SystemC();

Q: SystemC compile? http://funningboy.blogspot.com/2010/09/risc-cpu-systemc.html project https://github.com/funningboy/SOC_c_model/blob/master/Algorithm/Force_Directed_Scheduling/main.pl ps: future works 1.pipeline or parallel detected. 2.bus interface. 3.memory map location 4.processor element sharing