MYHDL example

底下是 ＭyＨＤＬ 的範例, 利用 Python 建立起一個符合 hardware simulation 的 IDE, 你可以發現有許多 sensitive trigger 的 functional block. 這有點類似 Verilog blocking/no-blocking 的語法, 讓 hardware designer 能夠很快速的上手. 且提供類似 core dump的機制, 讓使用者可以透過 waveform debug, 除此之外, 也可連接 Python 現有的 physical level driver. 達到 hardware/software co-simulation 的 virtual  platform.


主要功能
1. fetch all sequence trigger to sequence queue
2. sort queue by simulation time
3. put curent trigger to work queue
4. spawn each trigger from work queue
5. code gen if simulation requirement is pass

#!/usr/bin/python

from myhdl import *
import random

# operator map table
OP = { "ADD" : 0x00,
       "SUB" : 0x01,
       "MUX" : 0x02,
       "DIV" : 0x03,
       "RSHIFT" : 0x04,
       "LSHIFT" : 0x05 }

# DUT
def alu_0(clk, srst, z, x, y, op):
    """ alu  sensitive by positive edge clk syn rst """

    @always(clk.posedge)
    def ALU():
 if srst:
     z.next = 0
 else:
     if op == OP['ADD']:
  z.next = x + y
     elif op == OP['SUB']:
      z.next = x - y
     elif op == OP['MUX']:
      z.next = x * y

    return ALU


def test_alu_0():
    """ test DUT signal create TX/RX """

    # signal create
    clk = Signal(intbv(0, min=0, max=1))
    srst = Signal(intbv(0, min=0, max=1))
    z = Signal(intbv(0, min=0, max=64))
    y = Signal(intbv(0, min=0, max=32))
    x = Signal(intbv(0, min=0, max=32))
    op = Signal(intbv(0, min=0, max=6))

    op_count = Signal(intbv(0, min=0, max=32))

    # link DUT
    ptr_alu_0 = alu_0(clk, srst, z, x, y, op)

    # test clock gen
    @always(delay(10))
    def clkgen():
     clk.next = clk

    # test pattern gen
    @always(delay(20))
    def patgen():

     def iter_op():
        op = OP[OP.keys()[op_count]]
        inc_count = op_count + 1
         op_count.next = 0 if inc_count == len(OP) else inc_count
     return op

 op.next = iter_op()
     x.next = x + 1
     y.next = y + 2

    return ptr_alu_0, clkgen, patgen


def simulate(timesteps):
    """ start simulation """
    tb = traceSignals(test_alu_0)
    sim = Simulation(tb)
    sim.run(timesteps)

simulate(100)

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