UVM AXI BFM 1.0 release

supported list

• AXI3/AXI4 bus protocol
• out of order/ inorder transactions
• each write/read phase is independent
• addr/write/resp is independent
• interlevel
• split
• performance watch dog 
• protocol watch dog
• performance report
• MAX, AVG, MIN bus bandwidth
• through put
• transaction list(disassemble bus info)
•  virtual master
• define each phase delay(req to grant or each valid/ready) or drive trx out time stamp
• virtual slave
• define each phase delay(req to grant or each valid/ready) or drive trx out time stamp
• scoreboard
• check connection
• check the memory read write is pass when the read/write trx in the same address, the read trx must be finished first than write trx to avoid the overwrite the address issue.
• STL 
• user define TRX language
• SystemC analysis port 
• user can use analysis port to link third part debug model by using DPI interface like Verilog to SystemC  or Verilog to C/C++
• 
  
• https://github.com/funningboy/uvm_axi

UVM notes 2

• UVM reference flow
• UVM tutorial
• http://cluelogic.com/tag/vmm/UVM_AGENT
• virtual sequencer
• handle each sub sequencers when the platform contains multi sequences to drive the same DUT. 
• avoid race conditions,  transaction sequence, like multi threads system
•  ex:
•       jb_seq1 = same_flavored_jelly_beans_sequence::type_id::create( .name( "jb_seq1" ), .contxt( get_full_name() ) );
•       jb_seq2 = same_flavored_jelly_beans_sequence::type_id::create( .name( "jb_seq2" ), .contxt( get_full_name() ) );
•       case ( recipe )
•         LEMON_MERINGUE_PIE: begin
•            jb_seq1.flavor          = jelly_bean_transaction::LEMON;
•            jb_seq2.flavor          = jelly_bean_transaction::COCONUT;
•            jb_seq1.num_jelly_beans = 2;
•            jb_seq2.num_jelly_beans = 2;
• configure
• set  register , interface from top to down
• test_lib -> test_env -> test_cfg -> test_agent ... 
• ex:
•    initial begin
•       uvm_config_db#( virtual jelly_bean_if )::set
•          ( .cntxt( null ), .inst_name( "uvm_test_top" ), .field_name( "jb_if1" ), .value( jb_if1 ) );
•       uvm_config_db#( virtual jelly_bean_if )::set
•          ( .cntxt( null ), .inst_name( "uvm_test_top" ), .field_name( "jb_if2" ), .value( jb_if2 ) );
•       run_test();
•    end
• register abstract
• check register r/w limitation(only r/w), fields check, width check, coverage, assertion
• ex:
•       flavor = uvm_reg_field::type_id::create( "flavor" );
•       flavor.configure( .parent                 ( this ),
•                         .size                   ( 3    ),
•                         .lsb_pos                ( 0    ),
•                         .access                 ( "WO" ),
•                         .volatile               ( 0    ),
•                         .reset                  ( 0    ),
•                         .has_reset              ( 1    ),
•                         .is_rand                ( 1    ),
•                         .individually_accessible( 0    ) );
• 
  
• assertion
• 
  
• functional coverage

xilinx AXI interconnect

key notes

• cascade AXI bus if the input port > 4 (crossbar) multi to one
• traffic gen for DDR protocol (align burst length to 8), from AXI 2 DDR 
• example:
• 16 streams of 1920x1080 60/75p video information with up to 32 bits/pixel can be handled by a single 64-bit DDR3 interface
• VDMA
• Test Pattern Generators (TPGs) 
• Video Timing Control (VTC) 
•  On-Screen Display (OSD) 
• performance
• 622MB/s 
• 16 streams through memory, or nearly 9.95 GB/s (80 Gb/s)! This 18-port shared memory controller is used to support the 16 VDMA channels
• a memory clock speed of 800 MHz (1,600 MHz data rate).The primary internal AXI4 slave interface of the memory controller is operated at 200 MHz, using an AXI4 data width of 512 bits, supporting a theoretical maximum data bandwidth of 12.8 GB/s

refs: http://www.xilinx.com/support/documentation/white_papers/wp417-Xilinx-AXI4-Interconnects.pdfhttp://www.xilinx.com/support/documentation/application_notes/xapp521_XSVI_AXI4.pdf
http://www.xilinx.com/support/documentation/ip_documentation/ug761_axi_reference_guide.pdf

high level synthesis with Xilinx

key notes:

• write your struct ASIC c code, no class...., only for struct supported
• familiar hardware c (no hierarchal ptr, dynamic/static cast/ptr)
• implemented module select(architecture set)
• sub standard cell assign
•  like a+b  for operator "add", it can be "32bitAdd", or "64bitAdd" ...
• memory assign
• internal buffer, (asyn_fifo) for different clock interface
• for loop extend(unroll)
• like for (i=0; i < 2; i++), it will be extend to l0, l1, sequences for reschedule, if the data doesn't have any dependence in this loop, that can merge these two sequences in one parallel sequence. 
• resource constrain
• area constrain
• sub cell constrain
• timing constrain
• scheduling and binding
• pipeline
• implemented protocol interface
• AXI3/4 AXI stream
• transfer task assign
• req/grant
• burst ... ex: axi_bus_write(addr, [data,..]) => for axi burst write transfer 

• RTL code gen
• verilog/systemc
• report
• trade off
• performance/area
• simulation time estimation
• delay 
• area estimation
• size
• refs:
• http://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_2/ug902-vivado-high-level-synthesis.pdf
• http://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_2/ug871-vivado-high-level-synthesis-tutorial.pdf
• http://www.xilinx.com/support/answers/50929.html

uvm DVCON2011 notes

uvm sequence item

speed up your simulation !!

• keynotes
• no waveform dump
• no timing check
• using unit delay
• using virtual model without real physical model
• atomic test like selftest/unittest
• atomic integration test / merge only input/output modules in DUT
• using two stage 0/1 info without 4 stage info 0/1/X/Z
• using error count num to finish simulation (avoid a lots useless info)
• using assertion to check functional value

ref:
https://www.google.com.tw/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&ved=0CDIQFjAA&url=http%3A%2F%2Fwww.bawankule.com%2Fverilogcenter%2Ffiles%2FDVCon_Sim_Increase_paper.pdf&ei=bkGnUcOnKMWTiAeZroD4Bg&usg=AFQjCNEyEYLFxQb5Qo8XnYa3gLKppuIobw&sig2=GPKPKLOpKTZ3K4rmwZ571A
http://www.cadence.com/Community/forums/t/24886.aspx
http://www.synopsys.com/Tools/Verification/FunctionalVerification/Pages/VCS.aspx
http://www.deepchip.com/items/0385-03.html
http://www.cadence.com/community/forums/T/23927.aspx