speed up your simulation !!

• keynotes
• no waveform dump
• no timing check
• using unit delay
• using virtual model without real physical model
• atomic test like selftest/unittest
• atomic integration test / merge only input/output modules in DUT
• using two stage 0/1 info without 4 stage info 0/1/X/Z
• using error count num to finish simulation (avoid a lots useless info)
• using assertion to check functional value

ref:
https://www.google.com.tw/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&ved=0CDIQFjAA&url=http%3A%2F%2Fwww.bawankule.com%2Fverilogcenter%2Ffiles%2FDVCon_Sim_Increase_paper.pdf&ei=bkGnUcOnKMWTiAeZroD4Bg&usg=AFQjCNEyEYLFxQb5Qo8XnYa3gLKppuIobw&sig2=GPKPKLOpKTZ3K4rmwZ571A
http://www.cadence.com/Community/forums/t/24886.aspx
http://www.synopsys.com/Tools/Verification/FunctionalVerification/Pages/VCS.aspx
http://www.deepchip.com/items/0385-03.html
http://www.cadence.com/community/forums/T/23927.aspx