System Bus Bridge Emulator @ SystemC

Hi all, How to communicate each different clock domain IPs with bus architecture? i think bridge is a good answer for you, what's "Bridge" and what's the benefits? you can check it from ARM (AHB 2 APB BUS Bridge) or X86 (PCI 2 PCI BUS Bridge)...,that can help you to known why we use it and how it work... Ref: AHB to APB Bridge (AHB2APB) In here,we model the system bus bridge emulator @SystemC code,beware it only support High Speed bus 2 Low Speed bus, if you want the both sides supported, you can rewrite it in Low 2 High Case and reconstructed it again.In this "IP", we support some features below. features 1. Read/Write Buffers(FIFO) In FIFO design, it can save the transaction wait for bus requirement, and get the high utility with it. 2. Parallel tasks for High/Low Speed Bus transaction In Master/Slave had it's own state machine, and each communication would handle by Latch Design. Ref: 3. Read back preloaded In the Read/Write transaction you would find the Read transaction is a critical case, why ?... Because the data wouldn't been exist ready in Bridge, so we should ask again to get d it from another side's Slaves, and keep it in our Bridge Buffer until the New Read Request is hit. 4. write through it like a Cache design, it can store the common used data and map the whole Slaves directly, so it can save the request times and increase the bus performance. Ref: Cycle Chart http://spreadsheets.google.com/pub?key=0An5jh2lwIpeKdE9nQnJCME1UdnNicl9oYTJZNHpVN3c&hl=en&output=html source code download here.