ALU estimator @ RTL verilog

purpose: 在 RTL design 中,除了做 function 驗證之外, 如果我們能夠事先得知 ALU 的個數,那在synthesis 跟 area estimation 上就有些許的幫助. 可以在RTL level 得到這些 rough data 做簡略的架構分析跟 optimization. method: step 1.analysis time windows @ each always block, step 2.find the max ALU numbers in our definition(Add,Sub,Mul...) target: 找出在 Design 中所需要的 ALU 個數 sample code ps:這邊不考慮 carry && over float 的判斷

  always @(posedge clk or posedge rst )begin
       if( rst )begin
            out_a <= 0;
            tmp_a <= 0;
       end
       else  begin
            if( sel_1 =='b1 ) begin
                out_a <= in_a + in_b + 2;
            end
            else begin
                if( sel_2 ==1'b1 )begin
                    out_a <= in_a - in_b + tmp_a;
                    tmp_a <= in_a>>1;
                end
                else begin
                    out_a <= in_a>>1;
                end
            end
       end
  end

  always @(posedge clk or posedge rst )begin
     if( rst )begin
          out_b <= 0;
     end
     else begin
          if( out_b < 10 ) begin
              out_b <= out_b +1;
         end
     end

Results: 可發現在 always block 1 最少需要 2 個 ADD, always block 2 最少要 1 個 ADD, 但在 always block 彼此是獨立的條件下, 所以在這個 Design 下最少需要 2+1 個 ADD. 當然其他可以以此類推. 最後可以用 prime time 合成一個 sample ADD.把 sample ADD 的 Info 建成 table, 帶入你的 Design 就可以大概的得知 Design 的 Area. ADD-> @ always block -> block level -> counts$VAR1 = { '1' => { '4' => 1, '3' => 2 }, '2' => { '3' => 1 } }; SUB-> @ always block -> block level -> counts$VAR1 = { '1' => { '4' => 1 }, '2' => {} }; MUL-> @ always block -> block level -> counts$VAR1 = { '1' => {}, '2' => {} }; tool requirements: perl verilog package code download here. Refs: ESL Design Flow, peak power, NetWork on Chip @c,