UVM notes

UVM

• virtual interface
• interface define
• modports(define the port type for master/slave)
• master (input,output), slave(input, output)...
• task trigger
• task req;
  `uvm_info(get_full_name(),"start req",UVM_LOW);
  vif.req <= 1b'1;
  @(posedge vif.clk);
  while(!vif.ack) @(posedge vif.clk)
  vif.req <= 1'b0;
  `uvm_info(get_full_name(),"end req",UVM_LOW);
  end_task
• protocol assertion
• assert
• timing constrain
• setup time, hold time, sample rate, clock rate
• http://learn-systemverilog.blogspot.tw/2010/07/writing-systemverilog-assertion-for.html
• UVM_Transfer
• transfer type, contain definition
• common
• transaction id, transaction type, begin time, end time
• base extends common
• such as : address, RW type, Data byte array, burst size
• UVM_Agent
• support monitor, (driver, sequencer) if the active option is on
• UVM_monitor
• collect pin level info to transaction level info
• export transaction analysis port to TLM2.0 SystemC or scoreboard 
• protocol coverage like burst len need to support 1,2,4,8,16....
• UVM_driver
• driver the test sequence lib to virtual interface
• UVM_sequencer
• task item manager 
• sort the sequences by it's own priority or set it's dependence condition or it's spawn event
• UVM_scoreboard
• check transaction is completed from master to slave or slave to master
• UVM_test
• define testsuites like "read_after_write", "normal test", "critical test"...
• UVM_env
• test env build up.
• modules
• config
• module
• config address range, RGM
• transaction
• config type, info, address, data, len...
• system
• whole design config
• UVM_package
• pack lib 

Assertions

• coverage assertion
• coverage group
• FSM group
• pattern group
• functional assertion
• c/c++ co-sim 
• phase to phase check
• DPI wrapper interface
• SystemC TL0/TL1 co-sim
• use TLM2.0 analysis port export 
• protocol assertion
• req/grant
• @(posedge clk) req |-> [1:3]gt;