UVM systemverilog assertion(SVA)

• assertion
• assert in C/C++, pointer check 
• A *a = new A();
• assert(a!=NULL);
• a->do_some_thing()...
• main purpose
• performance hazards
• performance requirement throughput for real time issue
• wrong functionality
• functional error when the transaction is miss-match for each condition description
• Assertion active at both clock edges
• a2: assert property(@(posedge clk)a|->b[*8]); 
• Sequence used as clocking event 
• sequence s;
  @(posedge clk) a[*5];
  endsequence
  a3: assert property (@(s) b |-> ##3 c); 
• Complex Boolean expression used for clock 
• a5: assert property (@(clk iff en) p1);    
• Wrong argument type or size
• `ASSERTS_ONE_HOT(a7, {sig1, sig2, sig3} ...);    
• short circuit 
• function bit legal_state(
• bit [0:3] current, bit valid);
• a12: assert #0 (valid |-> current != '0);
• legal_state = valid && $onehot(current);
• endfunction
• …
• if (status || legal_state(valid, state)) 
  
• Action block without functional call
• `define MY_MUTEX(sig) \
• assert #0($onehot0(sig))
• always @(posedge clk) begin
• ...
• `MY_MUTEX(fsm_1_state)
• `MY_MUTEX(fsm_2_state); 
• end
• req/grant protocol check
• a14: assert property
• (@clk req |-> strong(##[1:$] gnt));
• assertion for coverage
• c16: cover property (@clk 
• (state==REQ)##1 (state==SEND));
•  possibly ignored assertions
• low coverage(pattern valid/invalid, critical case, how to inc the coverage value)
•