- a very useful script language for bus performance estimation and bus functional check
- example:
# read B uart 0; Reading offset 0 of uart – data = 0x1c # write B uart 4 bb; Writing 0xbb to offset 4 of uart # read B uart 8; Reading offset 8 of uart – data = 0x28 # write B mac 30 11; Writing 0x11 to offset 30 of mac # readcheck B mac 11; Reading offset 0 of mac Error: Expected data = 0x11, Actual data = 0x22 Test Failed, with 1 error
- advantage
- simple
- error check
- disadvantage
- no time stamp
- maybe it use ASAP(as soon as possible) methodology to transfer transactions, it means masters or slaves are not in busy status, or fetch/push buffers not full
- no atomic transfer
- if valid/ready is not continuous in the burst transaction, the interlevel transactions will happened,
- like A1(4), A2(4), A1 has burst 4 trxs, A2 has burst 4 trxs.
- A1(2), A2(2), A1(2), A2(2) => atomic transactions when the A1 or A2 has busy or error in the internal transaction.
2013年5月8日 星期三
Microsemi BFM script language
synplify + ise TCL xflow
http://outputlogic.com/xcell_using_xilinx_tools/74_xperts_04.pdf
https://github.com/dlitz/openmsp430/blob/master/core/synthesis/actel/synplify.tcl
https://github.com/martinjthompson/VHDL-compare/blob/master/Synplify/rev_1/run_ise.tcl
https://github.com/martinjthompson/VHDL-compare/tree/master/Synplify
https://github.com/zakiali/pocket_corr/blob/master/pfb_core/SgIseProject.tcl
2013年5月6日 星期一
SystemVerilog Unit test = SVUnit = TDD(test drivent Development of Verification IP)
SystemVerilog UVM Unit test framework
ex:
ref : http://www.agilesoc.com/svunit/
- Methodology
- get UVM domain class and register it to unit test list
- fetch runnable test suite from test list, the sorted priority is based on schedule manager definition
- collect test suite UVM report
- report pass/fail coverages
ex:
//************************************************************
// Test:
// xformation_test
//
// Desc:
// ensure that objects going through the simple model have
// their field property updated appropriately (multiply by
// 2)
//************************************************************
`SVTEST(xformation_test)
begin
simple_xaction in_tr = new();
simple_xaction out_tr;
void'(in_tr.randomize() with { field == 2; });
put_port.put(in_tr);
get_port.get(out_tr);
`FAIL_IF(in_tr.field != 2);
`FAIL_IF(out_tr.field != 4);
end
`SVTEST_END(xformation_test)
ref : http://www.agilesoc.com/svunit/
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