SystemVerilog Unit test = SVUnit = TDD(test drivent Development of Verification IP)

SystemVerilog UVM Unit test framework

• Methodology
• get UVM domain class and register it to unit test list
• fetch runnable  test suite from test list, the sorted priority is based on schedule manager definition
• collect test suite UVM report 
• report pass/fail coverages

ex:

 
  //************************************************************
  // Test:
  //   xformation_test
  //  
  // Desc:
  //   ensure that objects going through the simple model have                                                                                                                       
  //   their field property updated appropriately (multiply by
  //   2)
  //************************************************************
  `SVTEST(xformation_test)
    begin
      simple_xaction in_tr = new();
      simple_xaction out_tr;
 
      void'(in_tr.randomize() with { field == 2; }); 
 
      put_port.put(in_tr);
      get_port.get(out_tr);
 
      `FAIL_IF(in_tr.field != 2); 
      `FAIL_IF(out_tr.field != 4); 
    end 
  `SVTEST_END(xformation_test)

ref : http://www.agilesoc.com/svunit/