sytemverilog virtual interface setup time hold time check

we use systemveirlog virtual interface and simulator keys $setup, $hold to check the setup/hold time.

interface my_if #(c_clk_high_time = 5,
                  c_clk_low_time  = 5) (input clk, en);
  specify
    specparam clk_high_time = c_clk_high_time;
    specparam clk_low_time = c_clk_row_time;
    $setup(en, negedge clk, clk_high_time * 4 / 5);
    $hold(negedge clk, en, clk_low_time * 4 / 5);
  endspecify

endinterface;

or

module timing_checks_in_sv (input clk, data, ...); 
  ...
  event ev_data_delayed_toggled;
  
  always @(data)
  begin
    fork
    begin
      # tSetup;
      -> ev_data_delayed_toggled;
    end
    join_none
  end

  property setup_hold_time_checker;
    time curr_time;
    @(posedge clk) (1, curr_time = $time) |->
    @(ev_data_delayed_toggled) (($time - curr_time) > (tSetup + tHold)); // check data arrival time is meet $time - cur_time > (SetUp + Hold)
  endproperty : setup_hold_time_checker

  ASSERT_SETUP_HOLD: assert property setup_hold_time_checker;
endmodule 

ref :
http://learn-systemverilog.blogspot.tw/2010/07/writing-systemverilog-assertion-for.html
http://www.ee.ed.ac.uk/~gerard/Teach/Verilog/me5cds/me95rh.html