SystemVerilog parallel tasks by event trigger

SystemVeilog event trigger is implemented by event manager, that can define the dependences of parent and child tasks. and each tasks will be registered in event list when the building phase is done, after it, the task manager will sort event list by it's dependence or timing (such as E(timing(0)(0)), E(timing(1)(1)) E0 > E1, E0 will be run first than E1.

AXI write phase example. using delay constrain to define which one is first, which one is second

// @ write phase before write addr phase
// cfg.write_addr_delay = 10;
// cdg.write_data_phase = 0;


// @ write phase after write addr phase
// cfg.write_addr_phase = 0;
// cfg.write_data_phase = 10;

task run_phase();
  fork
    write_addr_phase();
    write_data_phase();
    get_next_trx();
  join
endtask


task get_next_trx();
  forever begin
    @(posedge vif.clk);
    if (sequencer.item.has_next_trx()) begin
      trx = sequencer.item.get_next_trx();
      if (trx.rw == `WRITE)
        -> start_write;
      else
        -> start_read;
    end 
  end 
endtask

task write_addr_phase();
  forever begin
    if (start_write.triggered) begin
      repeat(cfg.write_addr_delay) @(posedge vif.clk);
      // do write phase
    end 
  end 
endtask

task write_data_phase();
  forever begin
    if (start_write.triggered) begin
      repeat(cfg.write_data_delay) @(posedge vif.clk);
      // do data phase
  end 
endtask