Hi all,
this is an AHB Master emulator write in SystemC, it supports AHB Master Interface and protocol, such as " Burst type for single or package(1, 4, 8, 16) supported" , " Busy wait for current transaction" , "Response for error handle" ..., and you can easily package it with your IP by using sample Wrapper Interface such as "Ack" or "Valid" signals, this can be make sure the data is good and accessing is ok too.
In general design, we using the "Read Buff" and "Write Buff" interface to capture the asynchronous data . "CTL/state Machine" is our control status, it defines each function works and each data paths.
PS: this is only emulator model, not the official model for ARM company support, you can rewrite it in your requirement, and the configure and each model sets are already definition in our initial condition.
target :
in this platform, we use one Master and one Slave to recourse Read/Write tested without Arbiter detection.
sample Waveform:
sample code
AHB_BUS_MASTER.h
#include <systemc.h>
#include <iostream>
using namespace std;
#define WP_BUS_BUFF_DEP 32
enum WP_BUS_TRANSFER_TYPE{
WP_BUS_IDLE =0,
WP_BUS_BUSY =1,
WP_BUS_NONSEQ =2,
WP_BUS_SEQ =3,
WP_BUS_INI =4, // our define
};
SC_MODULE(AHB_BUS_MASTER) {
//=============================================
// Wrapper Interface / Bus Interface
//=============================================
sc_in<bool> HCLK; //Fm Gb
sc_in<bool> HRESTn; //Fm Gb
sc_in<bool> HGRANTx; //Fm Arbiter
sc_in<bool> HREADY; //Fm Slave
sc_in<sc_uint<2> > HRESP; //Fm Arbiter/Slave
sc_in<sc_uint<32> > HRDATA; //Fm Slave
sc_out<bool> HBUSREQx; //To Aribiter
sc_out<bool> HLOCKx; //To Aribiter
sc_out<sc_uint<3> > HTRANS; //
sc_out<sc_uint<32> > HADDR; //To Decoder
sc_out<bool> HWRITE;
sc_out<sc_uint<3> > HSIZE;
sc_out<sc_uint<5> > HBURST;
sc_out<sc_uint<4> > HPROT;
sc_out<sc_uint<32> > HWDATA;
sc_signal<sc_uint<3> > WP_BUS_CUR_ST;
sc_signal<sc_uint<3> > WP_BUS_NXT_ST;
sc_signal<bool> WP_BUS_START;
sc_signal<bool> WP_BUS_HWRITE;
sc_signal<sc_uint<3> > WP_BUS_HTRANS;
sc_signal<sc_uint<3> > WP_BUS_HSIZE;
sc_signal<sc_uint<32> > WP_BUS_INC_SIZE;
sc_signal<sc_uint<4> > WP_BUS_HPROT;
sc_signal<sc_uint<5> > WP_BUS_BURST_SIZE;
sc_signal<sc_uint<32> > WP_BUS_HADDR;
sc_signal<sc_uint<32> > WP_BUS_INX;
sc_signal<bool> WP_BUS_HBUSY;
sc_signal<sc_uint<32> > WP_BUS_RD_BUFF[WP_BUS_BUFF_DEP];
sc_signal<sc_uint<32> > WP_BUS_UPDT_RD_BUFF[WP_BUS_BUFF_DEP];
sc_signal<sc_uint<32> > WP_BUS_RD_INX;
sc_signal<sc_uint<32> > WP_BUS_WT_BUFF[WP_BUS_BUFF_DEP];
sc_signal<sc_uint<32> > WP_BUS_UPDT_WT_BUFF[WP_BUS_BUFF_DEP];
sc_signal<sc_uint<32> > WP_BUS_HADDR_BUFF[WP_BUS_BUFF_DEP];
sc_signal<sc_uint<32> > WP_BUS_UPDT_HADDR_BUFF[WP_BUS_BUFF_DEP];
int GB_RW_COT;
SC_CTOR(AHB_BUS_MASTER){
//=================================
// Wrapper / Bus Interface Function
//=================================
SC_METHOD(PRO_WP_BUS_ST);
dont_initialize();
sensitive << HRESTn;
sensitive << HCLK.pos();
SC_METHOD(PRO_WP_BUS_INI4SST);
dont_initialize();
sensitive << HCLK.pos();
SC_METHOD(PRO_WP_BUS_ST_DO);
dont_initialize();
sensitive << WP_BUS_CUR_ST;
sensitive << WP_BUS_START;
sensitive << HGRANTx;
sensitive << HREADY;
sensitive << HRESP;
sensitive << WP_BUS_HBUSY;
sensitive << WP_BUS_INX;
sensitive << WP_BUS_BURST_SIZE;
SC_METHOD(PRO_WP_BUS_ST_OT);
dont_initialize();
sensitive << WP_BUS_CUR_ST;
sensitive << WP_BUS_UPDT_HADDR_BUFF[0];
SC_METHOD(PRO_WP_BUS_UPDAT_WT_BUFF);
dont_initialize();
sensitive << HCLK.pos();
SC_METHOD(PRO_WP_BUS_UPDAT_HADDR_BUFF);
dont_initialize();
sensitive << HCLK.pos();
SC_METHOD(PRO_WP_BUS_UPDAT_HBUSY);
dont_initialize();
sensitive << WP_BUS_CUR_ST;
SC_METHOD(PRO_WP_BUS_UPDAT_RD_BUFF);
dont_initialize();
sensitive << HCLK.pos();
AHB_BUS_MASTER_VCD_DUMP();
GB_RW_COT =0;
};
void AHB_BUS_MASTER_VCD_DUMP();
void PRO_WP_BUS_INI4SST();
void PRO_WP_BUS_ST();
void PRO_WP_BUS_ST_DO();
void PRO_WP_BUS_ST_OT();
void PRO_WP_BUS_UPDAT_WT_BUFF();
void PRO_WP_BUS_UPDAT_HADDR_BUFF();
void PRO_WP_BUS_UPDAT_HBUSY();
void PRO_WP_BUS_UPDAT_RD_BUFF();
void PRO_WP_BUS_INC_SIZE();
};
AHB_BUS_MASTER.cpp
#include <systemc.h>
#include "AHB_BUS_MASTER.h"
#include "AHB.h"
void AHB_BUS_MASTER::PRO_WP_BUS_ST(){
sc_uint<3> TMP_NXT_ST = ( HRESTn.read()==false )? WP_BUS_INI : WP_BUS_NXT_ST.read();
WP_BUS_CUR_ST.write(TMP_NXT_ST);
}
void AHB_BUS_MASTER::PRO_WP_BUS_ST_DO(){
sc_uint<3> TMP_CUR_ST = WP_BUS_CUR_ST.read();
sc_uint<3> TMP_NXT_ST = WP_BUS_CUR_ST.read();
switch(TMP_CUR_ST){
case WP_BUS_INI : TMP_NXT_ST = ( WP_BUS_START.read() == true ) ? WP_BUS_IDLE : WP_BUS_INI; break;
case WP_BUS_IDLE : TMP_NXT_ST = ( HGRANTx.read() == true ) ? WP_BUS_NONSEQ : WP_BUS_IDLE; break;
case WP_BUS_NONSEQ : TMP_NXT_ST = ( HREADY.read() == true || HRESP.read() == AMBA_OKAY ) ? WP_BUS_SEQ :
( HREADY.read() == false && HRESP.read() == AMBA_ERROR ) ? WP_BUS_NONSEQ :
( HREADY.read() == false && HRESP.read() == AMBA_RETY ) ? WP_BUS_IDLE :
( HREADY.read() == false && HRESP.read() == AMBA_SPLIT ) ? WP_BUS_IDLE :
( WP_BUS_HBUSY.read() == true ) ? WP_BUS_BUSY : WP_BUS_NONSEQ; break;
case WP_BUS_SEQ : TMP_NXT_ST = ( (HREADY.read() == true || HRESP.read() == AMBA_OKAY ) && WP_BUS_INX.read() == WP_BUS_BURST_SIZE.read() ) ? WP_BUS_INI :
( HREADY.read() == false && HRESP.read() == AMBA_ERROR ) ? WP_BUS_SEQ :
( HREADY.read() == false && HRESP.read() == AMBA_RETY ) ? WP_BUS_IDLE :
( HREADY.read() == false && HRESP.read() == AMBA_SPLIT ) ? WP_BUS_IDLE :
( WP_BUS_HBUSY.read() == true ) ? WP_BUS_BUSY : WP_BUS_SEQ; break;
case WP_BUS_BUSY : TMP_NXT_ST = ( WP_BUS_HBUSY.read() == true )? WP_BUS_BUSY : WP_BUS_SEQ; break;
}
WP_BUS_NXT_ST.write(TMP_NXT_ST);
}
void AHB_BUS_MASTER::PRO_WP_BUS_ST_OT(){
sc_uint<3> TMP_CUR_ST = WP_BUS_CUR_ST.read();
sc_uint<2> TMP_HTRANS = WP_BUS_HTRANS.read();
sc_uint<32> TMP_HADDR = WP_BUS_UPDT_HADDR_BUFF[0].read();
sc_uint<3> TMP_HSIZE = WP_BUS_HSIZE.read();
sc_uint<5> TMP_BURST_SIZE = WP_BUS_BURST_SIZE.read();
sc_uint<4> TMP_HPROT = WP_BUS_HPROT.read();
sc_uint<32> TMP_HWDATA = WP_BUS_UPDT_WT_BUFF[0].read();
bool TMP_HWRITE = WP_BUS_HWRITE,read();
switch(TMP_CUR_ST){
case WP_BUS_INI : HTRANS.write(WP_BUS_INI); HBUSREQx.write(false); HLOCKx.write(false); break;
case WP_BUS_IDLE : HTRANS.write(WP_BUS_IDLE); HBUSREQx.write(true); HLOCKx.write(true); break;
case WP_BUS_NONSEQ: HTRANS.write(WP_BUS_NONSEQ); HBUSREQx.write(true); HLOCKx.write(true);
HWRITE.write(TMP_HWRITE);
HADDR.write(TMP_HADDR);
HSIZE.write(TMP_HSIZE);
HBURST.write(TMP_BURST_SIZE);
HPROT.write(TMP_HPROT); break;
case WP_BUS_SEQ : HTRANS.write(WP_BUS_SEQ); HBUSREQx.write(true); HLOCKx.write(true);
HADDR.write(TMP_HADDR);
HWDATA.write(TMP_HWDATA); break;
case WP_BUS_BUSY : HTRANS.write(WP_BUS_BUSY); break;
}
}
void AHB_BUS_MASTER::PRO_WP_BUS_UPDAT_HBUSY(){
sc_uint<3> TMP_CUR_ST = WP_BUS_CUR_ST.read();
( TMP_CUR_ST == WP_BUS_NONSEQ || TMP_CUR_ST == WP_BUS_SEQ )? WP_BUS_HBUSY.write(true) : WP_BUS_HBUSY.write(false);
}
void AHB_BUS_MASTER::PRO_WP_BUS_UPDAT_HADDR_BUFF(){
sc_uint<3> TMP_CUR_ST = WP_BUS_CUR_ST.read();
sc_uint<32> TMP_BURST_SIZE = WP_BUS_BURST_SIZE.read();
sc_uint<32> TMP_INX = WP_BUS_INX.read();
if( TMP_CUR_ST == WP_BUS_INI || HRESP.read()==AMBA_RETY || HRESP.read()==AMBA_SPLIT ){
for(unsigned int i=0; i < WP_BUS_BUFF_DEP; i++ ){ WP_BUS_UPDT_HADDR_BUFF[i].write( WP_BUS_HADDR_BUFF[i].read() ); }
TMP_INX = 0;
}else if( (TMP_CUR_ST == WP_BUS_NONSEQ || TMP_CUR_ST == WP_BUS_SEQ) && HREADY.read() == true && HRESP.read()==AMBA_OKAY ){
//update HADDR
for(unsigned int i=0; i < WP_BUS_BUFF_DEP-1; i++){ WP_BUS_UPDT_HADDR_BUFF[i].write( WP_BUS_UPDT_HADDR_BUFF[i+1].read() ); }
TMP_INX++;
}
WP_BUS_INX.write(TMP_INX);
}
void AHB_BUS_MASTER::PRO_WP_BUS_UPDAT_WT_BUFF(){
sc_uint<3> TMP_CUR_ST = WP_BUS_CUR_ST.read();
sc_uint<5> TMP_BURST_SIZE = WP_BUS_BURST_SIZE.read();
if( TMP_CUR_ST == WP_BUS_INI || HRESP.read()==AMBA_RETY || HRESP.read()==AMBA_SPLIT ){
for(unsigned int i=0; i < WP_BUS_BUFF_DEP; i++ ){ WP_BUS_UPDT_WT_BUFF[i].write( WP_BUS_WT_BUFF[i].read() ); }
}else if( ( TMP_CUR_ST == WP_BUS_SEQ) && WP_BUS_HWRITE.read() ==true && HREADY.read() == true && HRESP.read()== AMBA_OKAY ){
//update WRITE
for(unsigned int i=0; i < WP_BUS_BUFF_DEP-1; i++){ WP_BUS_UPDT_WT_BUFF[i].write( WP_BUS_UPDT_WT_BUFF[i+1].read() ); }
}
}
void AHB_BUS_MASTER::PRO_WP_BUS_UPDAT_RD_BUFF(){
sc_uint<3> TMP_CUR_ST = WP_BUS_CUR_ST.read();
sc_uint<5> TMP_BURST_SIZE = WP_BUS_BURST_SIZE.read();
sc_uint<32> TMP_BUS_RD_INX = WP_BUS_RD_INX.read();
sc_uint<32> TMP_HRDATA = HRDATA.read();
if( TMP_CUR_ST == WP_BUS_INI || HRESP.read()==AMBA_RETY || HRESP.read()==AMBA_SPLIT ){
for(unsigned int i=0; i < WP_BUS_BUFF_DEP; i++ ){ WP_BUS_UPDT_RD_BUFF[i].write( WP_BUS_RD_BUFF[i].read() ); }
TMP_BUS_RD_INX =0;
}else if( ( TMP_CUR_ST == WP_BUS_SEQ) && WP_BUS_HWRITE.read() ==false && HREADY.read() == true && HRESP.read()== AMBA_OKAY ){
WP_BUS_RD_BUFF[TMP_BUS_RD_INX++].write(TMP_HRDATA);
}
WP_BUS_RD_INX.write(TMP_BUS_RD_INX);
}
void AHB_BUS_MASTER::PRO_WP_BUS_INI4SST(){
sc_uint<3> TMP_CUR_ST = WP_BUS_CUR_ST.read();
int TMP_START = WP_BUS_OFF;
int TMP_SIZE = AMBA_TS_16;
int TMP_HWRITE = WP_BUS_ON;
int TMP_BURST_TYPE = AMBA_INC4;
int TMP_OFFSET = 0;
int TMP_SLAVE = 0;
if( TMP_CUR_ST == WP_BUS_INI ){
TMP_START = WP_BUS_ON;
TMP_SIZE = AMBA_TS_16;
TMP_HWRITE = ( GB_RW_COT ==0 )? WP_BUS_ON : WP_BUS_OFF;
TMP_BURST_TYPE = AMBA_INC4;
TMP_OFFSET = 1;
TMP_SLAVE = 0;
GB_RW_COT = (GB_RW_COT+1) %2;
cout << "BUS START ::\t" << TMP_START <<endl;
cout << "BUS HSIZE ::\t" << TMP_SIZE <<endl;
cout << "BUS HWRITE ::\t" << TMP_HWRITE <<endl;
cout << "BUS BURST_TYPE ::\t" << TMP_BURST_TYPE <<endl;
cout << "BUS SLAVE ::\t" << TMP_SLAVE << endl;
cout << "BUS SLAVE OFFSET::\t" << TMP_OFFSET <<endl;
// WP_BUS_START set
( TMP_START == WP_BUS_ON) ? WP_BUS_START.write(true): WP_BUS_START.write(false);
// CONTROL set
// WP_BUS_HSIZE we support the 32bit bus length
sc_uint<32> TMP_INC_SIZE = ( TMP_SIZE == AMBA_TS_8 ) ? 0x1 :
( TMP_SIZE == AMBA_TS_16 ) ? 0x2 :
( TMP_SIZE == AMBA_TS_32 ) ? 0x4 :
( TMP_SIZE == AMBA_TS_64 ) ? 0x8 :
( TMP_SIZE == AMBA_TS_128 ) ? 0x10 :
( TMP_SIZE == AMBA_TS_256 ) ? 0x20 :
( TMP_SIZE == AMBA_TS_512 ) ? 0x40 :
( TMP_SIZE == AMBA_TS_1024 ) ? 0x80 : 0x0;
WP_BUS_HSIZE.write(TMP_SIZE);
WP_BUS_INC_SIZE.write(TMP_INC_SIZE);
//WP_BUS_HPROT default set AMBA_DATA_ACCESS
WP_BUS_HPROT.write(AMBA_DATA_ACCESS);
//WP_BUS_HWRITE set
(TMP_HWRITE == WP_BUS_ON) ? WP_BUS_HWRITE.write(true): WP_BUS_HWRITE.write(false);
//WP_BUS_BURST set
sc_uint<5> BURST_SIZE = ( TMP_BURST_TYPE == AMBA_SIGNLE ) ? 1 :
( TMP_BURST_TYPE == AMBA_WRAP4 || TMP_BURST_TYPE == AMBA_INC4 ) ? 4 :
( TMP_BURST_TYPE == AMBA_WRAP8 || TMP_BURST_TYPE == AMBA_INC8 ) ? 8 :
( TMP_BURST_TYPE == AMBA_WRAP16 || TMP_BURST_TYPE == AMBA_INC16) ? 16: 0;
WP_BUS_BURST_SIZE.write(BURST_SIZE);
// random number 4 write out
if ( TMP_HWRITE == WP_BUS_ON){
for(unsigned int i=0; i < BURST_SIZE; i++){ WP_BUS_WT_BUFF[i].write( 10 + i); }
}
sc_uint<32> TMP_SOFFSET = (TMP_OFFSET == 0 )? WP_BUS_OFFSET_0 :
(TMP_OFFSET == 1 )? WP_BUS_OFFSET_1 :
(TMP_OFFSET == 2 )? WP_BUS_OFFSET_2 :
(TMP_OFFSET == 3 )? WP_BUS_OFFSET_3 : WP_BUS_OFFSET_D;
cout << "BUS SOFFSET ::\t" << TMP_SOFFSET <<endl;
sc_uint<32> TMP_HADDR = (TMP_SLAVE == 0 ) ? WP_BUS_SLAVE_0 + TMP_SOFFSET :
(TMP_SLAVE == 1 ) ? WP_BUS_SLAVE_1 + TMP_SOFFSET :
(TMP_SLAVE == 2 ) ? WP_BUS_SLAVE_2 + TMP_SOFFSET : WP_BUS_DEFAULT;
cout <<" BUS HADDR ::\t"<< TMP_HADDR<<endl;
// set INC/ WRAP initial ADDRESS if the HADDR is overflow
sc_uint<32> TMP_SHADDR = (TMP_HADDR & 0x0000000f) ;
cout <<" BUS SHADDR ::\t"<< TMP_SHADDR <<endl;
sc_uint<32> TMP_BOUND;
sc_uint<32> TMP_INC;
sc_uint<32> TMP_DEC;
TMP_BOUND = ( TMP_SHADDR =0x0 ) ? 16 :
( TMP_SHADDR =0x1 ) ? 15 :
( TMP_SHADDR =0x2 ) ? 14 :
( TMP_SHADDR =0x3 ) ? 13 :
( TMP_SHADDR =0x4 ) ? 12 :
( TMP_SHADDR =0x5 ) ? 11 :
( TMP_SHADDR =0x6 ) ? 10 :
( TMP_SHADDR =0x7 ) ? 9 :
( TMP_SHADDR =0x8 ) ? 8 :
( TMP_SHADDR =0x9 ) ? 7 :
( TMP_SHADDR =0xa ) ? 6 :
( TMP_SHADDR =0xb ) ? 5 :
( TMP_SHADDR =0xc ) ? 4 :
( TMP_SHADDR =0xd ) ? 3 :
( TMP_SHADDR =0xe ) ? 2 :
( TMP_SHADDR =0xf ) ? 1 : 0 ;
TMP_INC = TMP_BOUND/TMP_INC_SIZE-1;
cout << TMP_INC << endl;
TMP_DEC = BURST_SIZE - TMP_INC;
if ( TMP_BURST_TYPE == AMBA_SIGNLE ){
WP_BUS_HADDR_BUFF[0].write( TMP_HADDR );
} else if( TMP_BURST_TYPE == AMBA_WRAP4 ||
TMP_BURST_TYPE == AMBA_WRAP8 ||
TMP_BURST_TYPE == AMBA_WRAP16 ){ unsigned int j=0;
for( unsigned int i=0; i<TMP_INC; i++){
WP_BUS_HADDR_BUFF[j++].write( TMP_HADDR + i*TMP_INC_SIZE );
}
for( unsigned int i=TMP_DEC; i>0; i--){
WP_BUS_HADDR_BUFF[j++].write( TMP_HADDR -i*TMP_INC_SIZE );
}
} else if( TMP_BURST_TYPE == AMBA_INC4 ||
TMP_BURST_TYPE == AMBA_INC8 ||
TMP_BURST_TYPE == AMBA_INC16 ){
for(unsigned int i=0; i<BURST_SIZE; i++){
WP_BUS_HADDR_BUFF[i].write( TMP_HADDR + i*TMP_INC_SIZE );
}
}
cout <<"==================="<<endl;
}
}
void AHB_BUS_MASTER::AHB_BUS_MASTER_VCD_DUMP(){
sc_trace_file *fp = sc_create_vcd_trace_file("AHB_BUS_MASTER");
((vcd_trace_file*)fp)->sc_set_vcd_time_unit(-9);
sc_trace(fp, HCLK,"HCLK");
sc_trace(fp, HRESTn,"HRESTn");
sc_trace(fp, HGRANTx,"HGRANTx");
sc_trace(fp, HREADY,"HREADY");
sc_trace(fp, HRESP,"HRESP");
sc_trace(fp, HRDATA,"HRDATA");
sc_trace(fp, HBUSREQx,"HBUSREQx");
sc_trace(fp, HLOCKx,"HLOCKx");
sc_trace(fp, HTRANS,"HTRANS");
sc_trace(fp, HADDR,"HADDR");
sc_trace(fp, HWRITE,"HWRITE");
sc_trace(fp, HSIZE,"HSIZE");
sc_trace(fp, HBURST,"HBURST");
sc_trace(fp, HPROT,"HPROT");
sc_trace(fp, HWDATA,"HWDATA");
sc_trace(fp, WP_BUS_START,"WP_BUS_START");
sc_trace(fp, WP_BUS_CUR_ST,"WP_BUS_CUR_ST");
sc_trace(fp, WP_BUS_NXT_ST,"WP_BUS_NXT_ST");
sc_trace(fp, WP_BUS_HWRITE,"WP_BUS_WHRITE");
sc_trace(fp, WP_BUS_HTRANS,"WP_BUS_HTRANS");
sc_trace(fp, WP_BUS_HSIZE,"WP_BUS_HSIZE");
sc_trace(fp, WP_BUS_INC_SIZE,"WP_BUS_INC_SIZE");
sc_trace(fp, WP_BUS_HPROT,"WP_BUS_HPROT");
sc_trace(fp, WP_BUS_BURST_SIZE,"WP_BUS_BURST_SIZE");
sc_trace(fp, WP_BUS_HADDR,"WP_BUS_HADDR");
sc_trace(fp, WP_BUS_INX,"WP_BUS_INX");
sc_trace(fp, WP_BUS_HBUSY,"WP_BUS_HBUSY");
sc_trace(fp, WP_BUS_HADDR_BUFF[0],"WP_BUS_HADDR_BUFF_0");
sc_trace(fp, WP_BUS_HADDR_BUFF[1],"WP_BUS_HADDR_BUFF_1");
sc_trace(fp, WP_BUS_HADDR_BUFF[2],"WP_BUS_HADDR_BUFF_2");
sc_trace(fp, WP_BUS_HADDR_BUFF[3],"WP_BUS_HADDR_BUFF_3");
sc_trace(fp, WP_BUS_UPDT_HADDR_BUFF[0],"WP_BUS_UPDT_HADDR_BUFF_0");
sc_trace(fp, WP_BUS_UPDT_HADDR_BUFF[1],"WP_BUS_UPDT_HADDR_BUFF_1");
sc_trace(fp, WP_BUS_UPDT_HADDR_BUFF[2],"WP_BUS_UPDT_HADDR_BUFF_2");
sc_trace(fp, WP_BUS_UPDT_HADDR_BUFF[3],"WP_BUS_UPDT_HADDR_BUFF_3");
sc_trace(fp, WP_BUS_UPDT_WT_BUFF[0],"WP_BUS_UPDT_WT_BUFF_0");
sc_trace(fp, WP_BUS_UPDT_WT_BUFF[1],"WP_BUS_UPDT_WT_BUFF_1");
sc_trace(fp, WP_BUS_UPDT_WT_BUFF[2],"WP_BUS_UPDT_WT_BUFF_2");
sc_trace(fp, WP_BUS_UPDT_WT_BUFF[3],"WP_BUS_UPDT_WT_BUFF_3");
sc_trace(fp, WP_BUS_UPDT_RD_BUFF[0],"WP_BUS_UPDT_RD_BUFF_0");
sc_trace(fp, WP_BUS_UPDT_RD_BUFF[1],"WP_BUS_UPDT_RD_BUFF_1");
sc_trace(fp, WP_BUS_UPDT_RD_BUFF[2],"WP_BUS_UPDT_RD_BUFF_2");
sc_trace(fp, WP_BUS_UPDT_RD_BUFF[3],"WP_BUS_UPDT_RD_BUFF_3");
sc_trace(fp, WP_BUS_RD_INX,"WP_BUS_RD_INX");
sc_trace(fp, GB_RW_COT,"GB_RW_COT");
}
Results:
if you want to comiple the whole platfrom, you need download testbench and slave model in
here.
PS: this is only emulator model, not the official model for ARM company support, you can rewrite it in your requirement, and the configure and each model sets are already definition in our initial condition.
target :
in this platform, we use one Master and one Slave to recourse Read/Write tested without Arbiter detection.
sample Waveform:
sample code
AHB_BUS_MASTER.h
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