Multi-Core STA

相信有做過 DFT(design for testing)的人對 (STA) static timing report 應該不陌生.必須先透過 STA 把有效的 paths extract 出來.再把這些 path 餵到 ATPG (TMAX) 做 pattern gen 的動作. 底下就用 IC/CAD contest 的題目來做個簡單的 STA report. step flows 1. verilog parser parse verilog 2 our data based. 2. set timing constrain 2-1 require_time 2-2 slack time 3. run Multi core STA for timing report and input vectors. 3-1 pop up the top DFG graph. 3-1-1 DFG graph include "vertex, edge, logic, delay ..." types. 3-2 using the (BFS) search algorithm 3-2-1 finding the true && control path in each gate input and out logic. 3-3 using the (DFS) search algorithm 3-3-1 finding the valid path,which fit the timing constrain. 4. report the valid paths and input vectors. sample results:

{ Path 1 }
A true Path list {
=================================================
pin     type    incr    path_delay
=================================================
A[0]    (in)    0       0       r
U10/A   NAND2   0       0       r
U10/Y   NAND2   1       1       f
U9/A    NOT1    0       1       f
U9/Y    NOT1    1       2       r
U7/A    NAND2   0       2       r
U7/Y    NAND2   1       3       f
U4/A    NAND2   0       3       f
U4/Y    NAND2   1       4       r
M[1]    (out)   0       4       r
=================================================
Data Required time                      10
Data Arrival time                       4
=================================================
Slack                   6
}
Input Vector {
A[0]-TOP = r
A[1]-TOP = 0
B[0]-TOP = 0
B[1]-TOP = 1
}

project: https://github.com/funningboy/muti_sta