Isolation Cell Insertion for Low Power Design @ perl

在之前 post 中,探討過幾個比較高階的 low power design 技巧. learning plus: DVFS emulator learning plus: power management 4 Linux learning plus: ILP Scheduling with DVFS constrain @ perl learning plus: SmartReflex™ Power and Performance Management ... ... 這邊探討一下 Gate level design 的 lower power 技巧. isolation cell... what's isolation cell? Isolation cells are used to isolate the outputs at the output of the power domain. Power domain is a block in a design that can be switched off when it is not required. When a specific block is switched off, the outputs of the block will have X, if this value is propagated to switched on blocks, then it may lead to undesired behavior or chip failure. To avoid this, isolation cells be used to isolate the switched off block outputs. For example, for an AND gate, if you propagate this X value and if you make the other input of the AND gate to 0, then you will get known values at the power domain output, in the same way, if 1 is specified at other input of OR gate, then also we can get known values at the power domain outputs. Ref: [DFP] what is Isolation Cells? Low Power Flow 底下用 NCTU 大學部的專題 'Isolation Cell Insertion for Low Power Design' 當例子.不過想當初大學應該也做不出來吧...殘念 XD... top design flow 1. Verilog grammar 2. power grammar 3. ISORun 3-1 check power domain connected or not? 3-2 select the ISO type by constrain '-from -to' 3-3 modify the design 4. explore new verilog with ISO inserted and map reports check power domain connected or not? 1. -from case 1-1 find the deepest module by DFS search 1-2 pop back the module and check the output list exist or not? 2. -to case 2-1 find the deepest module by DFS search 2-2 pop back the module and check the input list exist or not? 3. top case 3-1 check the top module connected at "-from -to" constrain project : https://github.com/funningboy/iso_cell Ref: http://adar.ee.nctu.edu.tw/project.php