Path Delay Fault 4 ATPG Pt1

Pic Ref: http://www.wowcataclysminfo.com/wp-content/uploads/2009/09/wow-cataclysm-path-of-the-titans.jpg Path Delay Fault :

http://www.csee.umbc.edu/~cpatel2/links/418/lectures/chap12_lect11_delay_faults.pdf

constrain

(1) Gate Type "<" 10. we current support And(0), Or(1), Xor(2), Inv(3). ex : And -> Gate Type 0....

(2) Unit Delay each gate had the same delay time

(3) Input 2 Output would be blocked by flip-flop

make sure the the path is clear, not multi-cycle or false paths

Trace Methodology

using the Fan-in extraction to find out the "critical gate", that should be crossover by "slow path" and "fast path". because in the slow path part would usually happen "setup time violation", and fast path part would usually happen "hold time violation". so we should balance the design to meet both(setup time & hold time). in this reason, we can find out the time violation gate would be happen in the "critical path" and "fast path".

sample case: the red line is our critical path from input And1 to And3, the fast path is from And1 to And2, so in our methodology the violation may happen in gate Xor2.

Result :

sample download PS: the license is non-commercial use

http://sites.google.com/site/funningboy/perl_code/path_delay.rar?attredirects=0&d=1