uBoot Case Study @ omap3

在Booot的流程中, boot-loader 會先做些簡單的初始化, 如CPU/RAM set...and load Kernel imag to RAM,之後把使用權還給 Kernel build.會根據現有的Architecture 載入相對應的Driver 跟 configure 載入 root files,最後 run script 建立起 Application. 底下針對 u-boot-2010.06 OMP cotexA8 @beagle 來做說明. Step1. 在 uBoot 的 Flow 上中要先定義好 CPU && Board 的 Type 1.ARC -> CPU config ARM, X86, MIPS... 2.ARC -> Board config TI, ASUS... 這邊假設是用 CPU @ u-boot-2010.06/arch/arm/cpu/arm_cortexa8 Board @ u-boot-2010.06/board/ti/beagle Step2. uBoot loaded && LOW level set @ Arc/CPU 在 u-boot.lds 中會定義 bootload 的起始位置跟Entry point@ 0x00000000. and entry @ arm_cortexa8/start.o Ref: u-boot.lds

OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
        . = 0x00000000;

        . = ALIGN(4);
        .text   :
        {
                arch/arm/cpu/arm_cortexa8/start.o       (.text)
                *(.text)
        }

而在 start.s 中,主要透過Assembly code 來設定 @ARM CPU 基本的function Mode,跟load boot-loader 到 RAM 的動作. start.s

.globl _start
_start: b       reset
        ldr     pc, _undefined_instruction
        ldr     pc, _software_interrupt
        ldr     pc, _prefetch_abort
        ldr     pc, _data_abort
        ldr     pc, _not_used
        ldr     pc, _irq
        ldr     pc, _fiq

_undefined_instruction: .word undefined_instruction
_software_interrupt:    .word software_interrupt
_prefetch_abort:        .word prefetch_abort
_data_abort:            .word data_abort
_not_used:              .word not_used
_irq:                   .word irq
_fiq:                   .word fiq
_pad:                   .word 0x12345678 /* now 16*4=64 */

lowlevel_init.S 設定 hold chip 的 Freq. 包含 PLL set, Divide set, Mux set, Memory set, and PLL lock wait(等待 PLL 能穩定).

.globl lowlevel_init
lowlevel_init:
        ldr     sp, SRAM_STACK
        str     ip, [sp]        /* stash old link register */
        mov     ip, lr          /* save link reg across call */
        bl      s_init          /* go setup pll, mux, memory */
        ldr     ip, [sp]        /* restore save ip */
        mov     lr, ip          /* restore link reg */

        /* back to arch calling code */
        mov     pc, lr
....
pll_ctl_add:
        .word CM_CLKEN_PLL
pll_div_add1:
        .word CM_CLKSEL1_PLL

cache.S 中設定 Icache(instruction cache) && Dcache(data cache). 如 cache enable, cache disable, cache flush...

l2_cache_enable:
        stmfd   r13!, {r0, r1, r2, lr}
        @ ES2 onwards we can disable/enable L2 ourselves
        bl      get_cpu_rev
        cmp     r0, #CPU_3XX_ES20
        blt     l2_cache_disable_EARLIER_THAN_ES2
        mrc     15, 0, r3, cr1, cr0, 1
        orr     r3, r3, #2
        mcr     15, 0, r3, cr1, cr0, 1
        b       l2_cache_enable_END

step3. other sets GPIO, sys_info, syslib... 其實就是分別依序填入control value 到相對應的"control Register",能讓系統能做到簡單的work,之後在load kernel image, and build.... Refs : ARM cortexa8 beagle Refs: Das U-Boot -- the Universal Boot Loader Inside the Linux boot process Booting 基于S3C2410的Linux全线移植文档 作者：dozec U-Boot Quick Reference