Hi all,
We write a sample NOC emulator @ pthread c code. it support the multi tasks,such as Receiver and Transmitter at each Net-Nodes, and we add some ideas from
AXI Bus. we use two channels Design to handle the Address and Data Phase,that can increase the performance and reduce power consumed. But in current version we only support the Address Phase,you can add the Data phase detection in it.thx
1.NOC flow chart
Architecture.
Define the Architecture set(Map Table),it includes the connection of Net-Nodes and each Nodes information(FIFO INDEX, EMPTY, FULL)...
Task List
Define how many jobs should do..,and it includes our definition tags.
Node Trace
Tracing the next node and detecting finish or not.
NOC Architecture view
parts of network.c
void *SetAddrInf2NetNodeId_0(void *t){
int NodeId = (int)t;
int cot;
while( CheckOwnTaskListAddrDone(NodeId) == NET_FALSE ){
cot =3;
while( NetNode[NodeId].Addr_FULL == NET_TRUE ){
sleep( NetNode[NodeId].Addr_DELAY );
if( cot== 0 ){ printf("Out-of-Time Wait 4 NetNode Set Addr Phase @ %d \n",NodeId); break; }
cot--;
}
if( cot >0 ){
pthread_mutex_lock(&count_mutex);
if ( CheckTaskListAndSetAddrInf2NetNode(NodeId) == NET_OK_TASK ){
printf("Set TaskList 2 NetNode Ok @ %d \n",NodeId);
if(NET_DEBUG==0){ DisplayMapTable4NetNode();}
}
pthread_mutex_unlock(&count_mutex);
} else {
sleep( NetNode[NodeId].Addr_DELAY );
}
sleep( NetNode[NodeId].Addr_DELAY );
}
pthread_exit(NULL);
}
void *GetAddrInf2NetNodeId_0(void *t){
int NodeId = (int)t;
int cot;
while( CheckOwnTaskListAddrDone(NodeId) == NET_FALSE ){
cot =3;
while( NetNode[NodeId].Addr_EMPTY == NET_TRUE ){
sleep( NetNode[NodeId].Addr_DELAY );
if( cot== 0){ printf("Out-of-Time Wait 4 NetNode Get Addr Phase @ %d \n",NodeId); break; }
cot--;
}
if( cot >0 ){
pthread_mutex_lock(&count_mutex);
if (CheckAddrInfNetNode2TaskList(NodeId) == NET_OK_TASK ){
printf("Get NetNode 2 TaskList Ok @ %d\n",NodeId);
if(NET_DEBUG==0 ){ DisplayMapTable4NetNode(); }
if(TASK_DEBUG==0){ DisplayTaskList(); }
}
pthread_mutex_unlock(&count_mutex);
} else {
sleep( NetNode[NodeId].Addr_DELAY );
}
sleep( NetNode[NodeId].Addr_DELAY );
}
pthread_exit(NULL);
}
Results
Set TaskList 2 NetNode Ok @ 0
Get NetNode 2 TaskList Ok @ 0
TId :: 0,NId :: 4,FromAddr :: 400,ToAddr :: 400,RWType :: 5,DepTId :: -1,AddrDone :: 0
TId :: 1,NId :: 3,FromAddr :: 300,ToAddr :: 400,RWType :: 6,DepTId :: 0,AddrDone :: 1
TId :: 2,NId :: 7,FromAddr :: 700,ToAddr :: 800,RWType :: 6,DepTId :: -1,AddrDone :: 1
TId :: 3,NId :: 0,FromAddr :: 0,ToAddr :: 400,RWType :: 5,DepTId :: -1,AddrDone :: 1
---------------------------------------
Get NetNode 2 TaskList Ok @ 4
TId :: 0,NId :: 4,FromAddr :: 400,ToAddr :: 400,RWType :: 5,DepTId :: -1,AddrDone :: 0
TId :: 1,NId :: 3,FromAddr :: 300,ToAddr :: 400,RWType :: 6,DepTId :: 0,AddrDone :: 1
TId :: 2,NId :: 7,FromAddr :: 700,ToAddr :: 800,RWType :: 6,DepTId :: -1,AddrDone :: 1
TId :: 3,NId :: 0,FromAddr :: 0,ToAddr :: 400,RWType :: 5,DepTId :: -1,AddrDone :: 1
---------------------------------------
code download
here...
Refs:
NetWork on Chip @c
hi all,
If you are interest in the CPU architecture design,i think the 'rsic cpu' is a good choice.It is a sample package in systemc example, but it contain some problems with multi-drive. What's the multi-drive, it means the multi inputs drive the same output. you can image the data in this point is unstable, it should be 1 or 0 or x.... ,so the compiler would confuse what's the data in it.Because in systemc is no wire definition, in 'sc_signal' declare it like the register or buffer design, it would keep the current data until the next trigger to change it's data. we use a very sample way to avoid it, to create a new module and change the declare of 'sc_signal' to 'sc_in' and 'sc_out' . all new packages and version is release in here
please use this command to compile our package.
